[comp.lsi] Soft Error rates in dynamic RAM

mark@mips.UUCP (Mark G. Johnson) (09/25/87)

In article <1309@leo.UUCP>, larry@leo.UUCP (Larry Johnson) writes
	> I am in the process of designing a DRAM for a chip set and
	> need to determine the soft error rate. The data I can't seem
	> to get my hands on is the alpha particle flux rate caused by
	> the package lid and the metal traces on the wafer.

	> Does anyone out there have typical numbers for this, and does
	> anyone have any good reference papers they could recommend.
	> Better still, did any of you write a paper on SER?

The best single source is the proceedings of the IEEE International
Electron Devices Meetings ("IEDM").  I strongly recommend this paper:

	Dennis Segers et al., "Circuit Design Methodologies for the
	Reduction of Alpha Soft Error Rate", IEDM Technical Digest,
	December 1983, pp. 331-5.

as it covers design and test issues for modern (i.e. VCC/2 bitline) dRAMs.
-- 
-Mark Johnson	*** DISCLAIMER: The opinions above are personal. ***	
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