langlais@cg-atla.agfa.com (Ken Langlais) (03/20/90)
I would like to start a discussion on the topics of testability, boundary scan, and JTAG. If this discussion generates enough interest I will start a news group. I myself am just starting to look at boundary scan as a method of testing high density boards with surface mount technology. The only information I have been able to acquire is a booklet called Testability from TI. Is also speaks of IEEE 1149.1. When I did a call for a news group on this subject in news.groups I found out that the IEEE 1149.1 has been revised and is now 1149.3. Thankyou Ken -- ********************************************************** * Of all the things I lost, I miss my mind the most!!!!! * **********************************************************
grege@gold.GVG.TEK.COM (Gregory Ebert) (03/22/90)
In article <8491@cg-atla.agfa.com> langlais@cg-atla.agfa.com (Ken Langlais) writes: > > I would like to start a discussion on the topics of testability, > boundary scan, and JTAG. If this discussion generates enough interest > I will start a news group. I myself am just starting to look at > boundary scan as a method of testing high density boards with > surface mount technology. Being a chip designer, I must stress that boundary-scan testing is ONLY suitable for testing functionality, not speed. The plus side of boundary scan testing is that if the test is properly structured, it will do a great job at finding dead I/O's on chip, which account for the majority of system failures. IT CANNOT BE USED TO SCREEN UNTESTED I.C's IF YOU ARE LOOKING FOR ASSURING HIGH-QUALITY !!! One point worth mentioning is that you can do more damage than good if your test scheme causes parallel outputs to be driven simultaneously, or allows inputs to 'float'. This can cause excessive currents, which can cause electromigration, which causes long-term failures.