[comp.lsi] router effeciency

ram@shukra.Eng.Sun.COM (Renu Raman) (04/21/91)

We have some outside routers and some inhouse routers and am trying to
compare the relative effeciency of these routers.  One layman metric is
router efficiency which has been defined in atleast 2 different ways. I 
would like to know what is the common understand of it

  (This is mostly related to chip routers - specifically block routers)

  a) router efficiency: Ratio of routed area to total core area (where
     total core area is die size minus pad rings)
  b) router efficiency: Ratio of routed area to total block areas
     where block areas is sum of areas of the blocks in the core (not pad)

GIven (a) or (b) - first tell me which one is the correct one and then 
would like to know - what are the numbers for custom chips (probably manual)
semi-custom chips (using automatic block routers) for dice in the 12-15mm
range?

Thanks

renu raman
--
--------------------------------
   Renukanthan Raman				ARPA:ram@sun.com
   M/S 16-11, 2500 Garcia Avenue,               TEL :415-336-1813
   Sun Microsystems, Mt. View,  CA 94043