guilford@CSV.RPI.EDU.UUCP (04/10/87)
I hope someone can help me; I'm looking for information on hardware for testing chips. I am not looking for at-speed testing, and I am not looking for $30,000 - $60,000 industrial testers. What I am primarily interested in is a means of (under program control) driving some lines with a given set of vectors, reading the results of some pins, and dealing with some pins that both accept and generate data. I am considering building some hardware that would sit on an IBM PC bus and perform these functions, but it seems to me that it is not that uncommon of thing to want to do, and that there should either be products available to do this sort of thing, or other people who have in some other way solved a similar problem. Any information of where to look for products such as these, or other suggestions on how I can relatively cheaply (not $10,000's) test custom digital IC's would be appreciated. Thanks in advance for your efforts. I am Jim Guilford (guilford@csv.rpi.edu)
lechner@GULL.ULOWELL.EDU (Bob Lechner) (04/07/88)
I just read your msg. on vlsi network last year. How have yo made out on VLSI tester acq. or design? The organization m2c.m2c.org is buying testers of some type for MA. eng . schools. It may have info. Contact: pcohen or lipton@m2c.org I have ben trying to design a functional tester withg a PC host, in a comp eng course preceding a VLSI course. 30-50MHz clock rate, samppling scope approach to output data acquisition. Any ideas on this? RAM input at slower clock cycles, pattern generation within each cycle, video RAMS as data sources and sinks.
lechner@GULL.ULOWELL.EDU (Bob Lechner) (04/07/88)
I just read your msg. on vlsi network last year. How have yo made out on VLSI tester acq. or design? The organization m2c.m2c.org is buying testers of some type for MA. eng . schools. It may have info. Contact: pcohen or lipton@m2c.org I have ben trying to design a functional tester withg a PC host, in a comp eng course preceding a VLSI course. 30-50MHz clock rate, samppling scope approach to output data acquisition. Any ideas on this? RAM input at slower clock cycles, pattern generation within each cycle, video RAMS as data sources and sinks
paul@odin.m2c.org (Paul Cohen) (04/08/88)
In article <8804070200.AA04146@gull.ulowell.edu> lechner@GULL.ULOWELL.EDU (Bob Lechner) writes: >I just read your msg. on vlsi network last year. How have yo made out >on VLSI tester acq. or design? The organization m2c.m2c.org is buying >testers of some type for MA. eng . schools. It may have info. >Contact: pcohen or lipton@m2c.org Just a correction: I am cohen@m2c.org, not pcohen. I haven't got much info worth writing for yet, but if there is interest, I'll post what we find out later. Paul Paul B. Cohen Massachusetts Microelectronics Center cohen@m2c.org Westborough, MA cohen%m2c.m2c.org@relay.cs.net {harvard,ulowell,frog,umvlsi}!m2c!cohen