grout@sunspot.cad.mcc.com (Steve Grout) (07/14/88)
This is to note that the availability of Chapter 04 of a
1076-1987 VHDL test suite which was translated from an 7.2 VHDL
version test suite developed by Intermetrics under funding by the
DoD.
These tests for Chapter 04 of the VHDL LRM have been posted to
the VHDL software repository, vhdl-sw@simtel20.arpa. You may retrieve
them from there or make a request to us for an email copy of a 'shar'
file from which you can obtain all of the tests.
Included below is a summary by paragraph and test file name
of what each test does.
These tests have been verified todate mainly against a VHDL
'recognizer' so they may yet have problems with VHDL semantics.
They consist of two classes of tests,
ERROR Tests: - those which start with 'e' should result in VHDL errors
at the spot in them where there is a comment about error being expected.
SIMPLE Tests: - those which start with 's' should analyze or compile cleanly.
These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to
make sure our various VHDL CAD tools work correctly.
Your comments and especially constructive criticism is urgently requested
via any way we can get it. All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.
Thanks for your support!
--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com
---------------------- TEST SYNOPSIS ---------------------------------
------------------------------------------------------------------------
Chapter: 04-Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
Paragraph: Declarations - 5.0 --> 4.0"
------------------------------------------------------------------------
------------------------------------------------------------------------
Paragraph: Types - 5.1 --> 4.1"
------------------------------------------------------------------------
------------------------------------------------------------------------
Paragraph: Type Declarations - 5.1.1 --> 4.1"
------------------------------------------------------------------------
Test: e-04-1-0-0001a.vhdl
-- Check that types created by distinct type definitions are distinct types.
-- That is, check that an object of type X is not compatible with an object of
-- type Y even if the type declarations for X and Y are textually identical
-- (aside from the names X and Y).
------------------------------------------------------------------------
Paragraph: Subtype Declarations - 5.1.2 --> 4.2"
------------------------------------------------------------------------
Test: e-04-2-0-0001a.vhdl
-- Check that an index constraint must not appear in a subtype indication if the
-- type mark already imposes an index constraint. Check for subtype declarations
-- and for object declarations.
Test: e-04-2-0-0002a.vhdl
-- Check that a type mark must denote either a type or a subtype.
Test: s-04-2-0-0001a.vhdl
-- Check that subtypes of subtypes may be declared to any depth; that is, the
-- type mark in a subtype indication may itself be a subtype.
Test: s-04-2-0-0002a.vhdl
-- Check that the constraint in a subtype indication is optional (except that an
-- index constraint may not appear in a subtype indication if the type mark
-- already imposes an index constraint).
Test: s-04-2-0-0003a.vhdl
-- Check that the base type of a subtype is the base type of the type or subtype
-- in the subtype indication (that is, the base type of a subtype is not always
-- the type mark in the subtype indication). Check using the base attributes.
Test: s-04-2-0-0004a.vhdl
-- Check that a subtype declaration does not define a new type
-- (that is, two operands of different subtypes of the same type are
-- also of the same base type). Check using the equality operator between
-- two objects, one of subtype s1 of T and the other of subtype s2 of t;
Test: s-04-2-0-0005a.vhdl
-- Check that a characteristic indication is optional in a subtype
-- indication. Check for signal and non-signal objects.
Test: s-04-2-0-0006a.vhdl
-- Check that a subtype indication does NOT inherit the characteristics of
-- its type mark. That is, check that a subtype is granular even if its
-- type mark is the name of an atomic signal.
Test: s-04-2-0-0007a.vhdl
-- Check that the direction of a scalar subtype indication which contains
-- a range constraint is the direction of its range constraint;
Test: s-04-2-0-0008a.vhdl
-- Check that the direction of a scalar subtype indication is ascending
-- if it contains no range constraint.
Test: s-04-2-0-0009a.vhdl
-- Check that a characteristic indication has no effect on objects
-- which are not signals.
------------------------------------------------------------------------
Paragraph: Objects - 5.2 --> 4.3"
------------------------------------------------------------------------
------------------------------------------------------------------------
Paragraph: Object Declarations - 5.2.1 --> 4.3.1"
------------------------------------------------------------------------
Test: e-04-3-1-0001a.vhdl
-- Check that a default expression in an object declaration must be a generic
-- expression.
Test: e-04-3-1-0002a.vhdl
-- Check that the subtype of the default expression in an object declaration
-- must be the same or convertable to the subtype of the object.
Test: e-04-3-1-0003a.vhdl
-- Check that a constant declaration must contain an explicit default
-- expression.
Test: e-04-3-1-0004a.vhdl
-- Check that the reserved word "static" may only appear in a
-- variable declaration.
Test: e-04-3-1-0005a.vhdl
-- Check that boxes may not occur in object declarations.
Test: e-04-3-1-0006a.vhdl
-- Check that a signal or alias declaration must not contain a
-- default expression.
Test: s-04-3-1-0001a.vhdl
-- Check that the default expression is optional for variable declarations.
Test: s-04-3-1-0002a.vhdl
-- Check that the reserved word " STATIC" is optional in variable declarations.
Test: s-04-3-1-0003a.vhdl
-- Check that the name specified in an alias declaration may itself be an alias.
Test: s-04-3-1-0004a.vhdl
-- Check that a multiple object declaration is equivalent to a sequence of the
-- corresponding number of single object declarations.
-- Check also identifier lists of element declarations, subprogram parameter
-- specifications, generic formal parameter specifications, and port
-- declarations.
------------------------------------------------------------------------
Paragraph: Constant Declarations - 5.2.1.1 --> 4.3.1.1"
------------------------------------------------------------------------
Test: e-04-3-1-1001a.vhdl
-- Check that the value of a constant cannot be modified after initiazation.
Test: e-04-3-1-1002a.vhdl
-- Check that formal subprogram parameters of mode "in", ports of mode "in",
-- formal generics, loop index within the corresponding loop, generate
-- index within the corresponding generate statement, subelement or slice of a
-- declared constant, and a concatenation of constants are all constants.
------------------------------------------------------------------------
Paragraph: Signal Declarations - 5.2.1.2 --> 4.3.1.2"
------------------------------------------------------------------------
Test: e-04-3-1-2001a.vhdl
-- Check that a subelement of an atomic signal must not appear on the left
-- hand side of a signal assignment statement.
Test: e-04-3-1-2002a.vhdl
-- Check that only a signal which is a bus may have more than
-- one source within the expanded test of a description.
Test: e-04-3-1-2003a.vhdl
-- Check that the atomic subelements of an atomic composite type
-- must be of a scalar type.
Test: e-04-3-1-2004a.vhdl
-- Check that a bus resolution functioon must take as input an
-- unconstrained array whose element type is the type of the bus.
Test: e-04-3-1-2005a.vhdl
-- Check that a bus resolution function must return a value of the
-- same type as the bus.
Test: e-04-3-1-2006a.vhdl
-- Check that subelements of a bus must not also be a bus.
Test: s-04-3-1-2001a.vhdl
-- Check That a subelement of a composite signal is also a signal.
Test: s-04-3-1-2002a.vhdl
-- Check that the function name is optional in a subtype indication
-- which contains a characteristic indication.
Test: s-04-3-1-2003a.vhdl
-- Check that an atomic signal may have more than one source.
Test: s-04-3-1-2004a.vhdl
-- Check that subelements of an atomic signal can be read
------------------------------------------------------------------------
Paragraph: Variable Declarations - 5.2.1.3 --> 4.3.1.3"
------------------------------------------------------------------------
Test: e-04-3-1-3001a.vhdl
-- Check that formal procedure parameters of modes "out" or "inout" are
-- variables.
------------------------------------------------------------------------
Paragraph: File Declarations - --> 4.3.2"
------------------------------------------------------------------------
echo " (...No tests available from 7.2 suite.) "
------------------------------------------------------------------------
Paragraph: Interface Declarations - --> 4.3.3"
------------------------------------------------------------------------
Test: e-04-3-3-0001a.vhdl
-- Check that index constraints and range constraints are not permitted in local
-- port lists.
Test: e-04-3-3-0002a.vhdl
-- Check that the same identifier may not be used to name more than one element
-- in an interface list.
Test: e-04-3-3-0003a.vhdl
-- Check that a default expression is allowed in subprogram parameters interface
-- elements of mode "in" only. Check for interface elements of other modes.
Test: e-04-3-3-0004a.vhdl
-- Check that the type of the default expression must be compatible with the
-- type of the port.
Test: e-04-3-3-0005a.vhdl
-- Check that a default expression must be a static expression.
Test: e-04-3-3-0006a.vhdl
-- Check that interface elements of mode "in" cannot be updated.
Test: e-04-3-3-0007a.vhdl
-- Check that the only reading permitted for interface elements of mode
-- "out" is of attributes other than STABLE, QUIET, DELAYED and LAST_VALUE.
Test: e-04-3-3-0008a.vhdl
-- Check that only interfaces elements which are signal are permitted to
-- have mode "buffer" or mode "linkage".
Test: e-04-3-3-0009a.vhdl
-- Check that interface elements of mode "buffer" must not be updated by
-- multiple signal assignment statements or associations.
Test: e-04-3-3-0010a.vhdl
-- Check that if an interface appears, it must not be empty (ie. empty pair
-- of paranthesis)
Test: e-04-3-3-0011a.vhdl
-- Check that reading and updating of interface elements of mode
-- "linkage" is permitted only in the case when it appears as an actual
-- signal that corresponds to an interface element of mode "linkage".
Test: e-04-3-3-0012a.vhdl
-- Check that attributes of interface elements of mode "linkage"
-- cannot be read.
Test: e-04-3-3-0013a.vhdl
-- Check that when no mode is explicitly given mode "in" is assumed.
Test: s-04-3-3-0001a.vhdl
-- Check that in interface lists all modes may be "in" or all modes"out".
Test: s-04-3-3-0002a.vhdl
-- Check that an interface list may be a list with
-- only one element.
Test: s-04-3-3-0003a.vhdl
-- Check that all types are legitimate in interface lists.
Test: s-04-3-3-0004a.vhdl
-- Check that an interface list may be declared with a large number (65) of
-- elements.
Test: s-04-3-3-0005a.vhdl
-- Check that mode is optional. If no mode is given
-- "In" is assumed.
Test: s-04-3-3-0006a.vhdl
-- Check that attributes and values of associated actuals of interface
-- elements of mode "in", "inout" and "buffer" can be read.
Test: s-04-3-3-0007a.vhdl
-- Check that reading attributes of interface elements of mode "out"
-- is permitted for attributes other than STABLE, QUIET, DELAYED and LAST_VALUE.
Test: s-04-3-3-0008a.vhdl
-- Check that multiple signal assignment statements and association lists
-- are permitted for updating interface elements of type signal and modes
-- "out" or "inout".
Test: s-04-3-3-0009a.vhdl
-- Check that updating of interface elements of mode "buffer" is permitted.
Test: s-04-3-3-0010a.vhdl
-- Check that reading and updating of interface elements of mode "linkage"
-- is permitted for actual signals corresponding to interface elements of
-- mode "linkage".
Test: s-04-3-3-0011a.vhdl
-- Check that default expressions are optional for interface elements of mode
-- "in" in subprograms parameter interface list, formal generic lists, and
-- formal part lists.
------------------------------------------------------------------------
Paragraph: Interface Lists - 5.2.2 --> 4.3.3.1"
------------------------------------------------------------------------
( No tests available from 7.2 suite.)
------------------------------------------------------------------------
Paragraph: Association Lists - --> 4.3.3.2"
------------------------------------------------------------------------
( No tests available from 7.2 suite.)
------------------------------------------------------------------------
Paragraph: Alias Declarations - 5.2.1.4 --> 4.3.4"
------------------------------------------------------------------------
Test: e-04-3-4-0001a.vhdl
-- Check that an alias declaration is only permitted in an interface
-- declaration, a next_level_configuration, a subprogram declaration,
-- a block, or in a package.
-- That is check that alias declarations are not permitted in process
-- statements.
Test: e-04-3-4-0002a.vhdl
-- Check that in an alias declaration, for each element in the subtype
-- indication there must be a matching element in the name and that for each
-- element in the name there must be a matching element in the subtype
-- indication.
Test: e-04-3-4-0003a.vhdl
-- Check that the identifer specified in an alias declaration denotes
-- the alias name only where both are visible
Test: e-04-3-4-0004a.vhdl
-- Check that the name in an alias decl must be the static
-- name of a visible object.
Test: e-04-3-4-0005a.vhdl
-- Check that the subtype indication must denote a generic subtype.
Test: s-04-3-4-0001a.vhdl
-- Check that the identifier specified in an alias declaration denotes
-- the alias name everywhere both are visible.
Test: s-04-3-4-0002a.vhdl
-- Check that the name in an alias declaration may denote a constant,
-- a variable, a signal, a formal port, a formal generic, a formal
-- subprogram parameter, or an element or slice of another object.
Test: s-04-3-4-0003a.vhdl
-- Check that the subtype indication in an alias declaration may specify
-- a different direction from that specified in the declaration of the
-- object it denotes.
------------------------------------------------------------------------
Paragraph: Attribute Declarations - 5.3, 5.3.1-2 --> 4.4"
------------------------------------------------------------------------
Test: e-04-4-0-0001a.vhdl
-- Check that predefined attributes which denote signals must
-- not be driven.
e-04-4-0-0001b.vhdl
Test: e-04-4-0-0002a.vhdl
-- Check that a user_defined attribute of a port, variable, or
-- constant of some composite type is an attribute of the entire object
-- not of its elements.
Test: s-04-4-0-0001a.vhdl
-- Check that an item inherits an attribute if the declaration of the entity
-- is accompanied by an attribute specification and if the entity belongs to
-- one of the classes in the entity class list of the attribute declaration.
Test: s-04-4-0-0002a.vhdl
-- Check that all types (scalar, composite) are permitted in attribute
-- declarations.
Test: s-04-4-0-0003a.vhdl
-- Check that the same attribute can be used for several entity classes.
Test: s-04-4-0-0004a.vhdl
-- Check that an attribute of an object applies to any alias of the object as
-- well as to the the object name declared in the object declaration. Check
-- for aliases which follow the attribute specification and that naming
-- an alias in the attribute specifications entity name list.
------------------------------------------------------------------------
Paragraph: Component Declarations - 5.4 --> 4.5"
------------------------------------------------------------------------
Test: e-04-5-0-0001a.vhdl
-- Check that the only object class allowed in a local port
-- list is signal.
Test: e-04-5-0-0002a.vhdl
-- Check that the only object class allowed in a local generic
-- list is constant.
Test: e-04-5-0-0003a.vhdl
-- Check that the only mode allowed in a local generic
-- list is in.
Test: e-04-5-0-0004a.vhdl
-- Check that default expressions are not permitted in local generic or
-- local port lists.
Test: s-04-5-0-0001a.vhdl
-- Check that if class is not specified in a local port
-- list then signal is assumed.
--
Steve Grout @ MCC VLSI CAD Program, Austin TX. [512] 343-0860
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout