rodb@coho.UUCP (Rod Barman) (12/10/88)
I recently read somewhere a blurb about a 32 by 32 processor array designed at Hughes. The array is composed of multiple wafers, each one bit-slice, sandwiched together vertically. If somebody knows of any references, I would appreciate a message. Thanks in advance, -- Rod Barman, Dept. of E.E., University of British Columbia CDN : rodb@ee.ubc.ca UUCP : ..!ubc-vision!ee.ubc.ca!rodb CSNET : rodb%ee.ubc.ca%ean.ubc.ca@RELAY.CSNET
aboulang@bbn.com (Albert Boulanger) (12/11/88)
"The Third Dimension", Michael Little & Jan Grinberg, Byte, November 88, 311-319 Albert Boulanger BBN Systems & Technologies Corp. aboulanger@bbn.com
moreno@maui.cs.ucla.edu (Jaime Moreno) (12/11/88)
The upcoming International Conference on Wafer Scale Integration
(January 3-5, San Francisco) will have three papers on the topic:
- The 3-D Computer
- Reliability of the 3-D Computer under stress of mechanical
vibration and thermal cycling
- Redundancy for yield enhancement in the 3-D computer
The three papers are from people at Hughes Research labs.
Jaime Moreno
-------------------------
Internet: moreno@CS.UCLA.EDU
UUCP: ...!{ihnp4,ucbvax,sdcrdcf,trwspp,randvax,ism780}!ucla-cs!morenoenbody@cpswh.cps.msu.edu (Dr Richard Enbody) (12/15/88)
In article <18778@shemp.CS.UCLA.EDU> moreno@cs.ucla.edu (Jaime Moreno) writes: >The upcoming International Conference on Wafer Scale Integration >(January 3-5, San Francisco) will have three papers on the topic: > >The three papers are from people at Hughes Research labs. > I am very interested in this topic, but I am not going to the conference. Is there anyone from Hughes reading this who could email (or mail) copies or tell me who to contact for copies? Thank you, rich enbody