mark@mips.COM (Mark G. Johnson) (03/24/89)
A useful table appeared in EE TIMES, (20 Mar 1980) page T18 --
"Chip sans killer defects". It provides a relatively unbiased
projection of current and future state of the art in MOS manufacturing
yields.
Basically, chip yield falls off exponentially as (A * D), where A is
the die area and D is a measure of the dirtyness of the fab (the "defect
density"). The article provides values of D for various years,
both past and future. Note that these are just one author's *opinion*
of defect density; tain't necessarily correct. Nevertheless the
projections are useful for provoking amusing discussions:
Year 1984 1987 1989 1992
Defect density [cm^(-2)] 1.83 1.16 0.72 0.38
If these are correct (a *big* if, not a given at all...) then one can
prognosticate about yields of current and future MOS microprocessors.
Just for a grin, let's look at two different die sizes: a 10x15 millimeter
chip, and a really monstrous big chip having 50% more area at 15x15.
(recall the i860 is 10x15). Let's assume 6 inch wafers:
Defect # Die sites on Percent # Good
Die Year Density a 6-inch wafer Yield Die
-----------------------------------------------------------------------
10x15 1987 1.16/cm2 85 18 % 15
10x15 1989 0.72/cm2 85 34 % 28
15x15 1987 1.16/cm2 49 7.4 % 3
15x15 1989 0.72/cm2 49 20 % 9
So we can see that right now, today, 1Q-1989, the industry ought to be
able to get 15-28 defect-free, i860-sized microprocessor dice per
wafer. Furthermore, we could design a bigger chip having 50% more area
(15mm x 15mm) and still produce 3 to 9 defect-free microprocessor dice.
(mounting the soapbox)
This is, of course, only useful to estimate whether or not a
chip is manufacturable. If the expected yield is *extremely* small
(say, below 1 die/wafer), we'd have to be very worried. But,
with an expected 3-to-9 die, we'll get a relatively smooth flow
of good chips from the fab.
What yield is *NOT* good for, is estimating product cost. It
only measures die cost. To that you must add test cost(s),
burn-in cost, depreciation on the $100M fab, depreciation on
the array of $5M testers, package cost, QA and Reliability
screen costs, design cost, and so forth. Particularly for
microprocessors, die cost is a *negligible* fraction of
selling price.
(dismount)
So we can conclude that (*if* the defect density numbers in EE TIMES
are correct) "reasonable" folks who want guaranteed steady flow of
die can build them at 15x15 millimeters, today, in 1989.
{Note: in the table above, percent yield was calculated using the
"Poisson" model, which is known to be rather pessimistic. According
to this model, percent yield == exp( -1.0 * A * D ). In practice it
is usually observed that yields are higher than the Poisson model
predicts. There are more accurate, more complicated models available
but this one is the most well-known formula.}
--
-- Mark Johnson
MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
...!decwrl!mips!mark (408) 991-0208perley@trub.steinmetz (Donald P Perley) (03/30/89)
In article <15878@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: > > > What yield is *NOT* good for, is estimating product cost. It > only measures die cost. To that you must add test cost(s), > burn-in cost, depreciation on the $100M fab, depreciation on > the array of $5M testers, package cost, QA and Reliability > screen costs, design cost, and so forth. Particularly for > microprocessors, die cost is a *negligible* fraction of > selling price. Many of the additions you list are dependant on the number of dice made, but have to be ammortized over the number sold (the good ones), so yield is significant, at least far as fab line and tester ammortization is concerned. The cost of a good die includes what it cost to send its share of bad ones throught the fab, and the bad ones still get tested.
waters@dover.sps.mot.com (Mike Waters) (03/30/89)
In article <13481@steinmetz.ge.com> perley@trub.steinmetz.ge.com (Donald P Perley) writes: >In article <15878@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >> What yield is *NOT* good for, is estimating product cost. It >> only measures die cost. To that you must add test cost(s), >Many of the additions you list are dependant on the number of dice made, >but have to be ammortized over the number sold (the good ones), so >yield is significant, at least far as fab line and tester ammortization >is concerned. The numbers are different again if you look at system costs, e.g. a Macintosh vs the cost of the microprocessor chip. Case in point, the IBM PC uses an Intel microprocessor, but Motorola had the highest "value added" in the original box since the entire power supply used Motorola parts! The I/O is also Moto, but that too is a small part of the cost. A larger system like a Sun or Apollo has most (~80%) in just bulk memory. Very low cost/markup, but still the bulk of the cost. Add that to system testing, software, and distribution and the actual die cost gets lost in the noise.
jose@euteal.euteal.uucp (& Pineda) (04/02/89)
When talking about defects one must specify what kind of defects :
Spot defects ? Global deformations (under/over etching) ? Crystal
dislocations ? Process related ? etc, etc, etc. If assuming that the
mentioned defects are spot defects, then what kind of spot defects :
missing material ? extra material ? in what layer ? Furthermore,
defects have to be characterized according to : type, size, frequency
of occurrence. Thus, a defect size distribution is needed. Modern
yield prediction does not only take an IC as a black box in which
defects are placed. In fact if one looks inside of the "black box"
there are many places where the defects are less likely to damage the
IC. For instance, empty regions, bonding pads, etc, etc, etc. Assume
that we are dealing with spot defects. Whether a fault can occur or
not, depends on the critical area of the related patterns. The
critical area is the area where the center of a defect must fall to
introduce a fault. Primitive faults at the IC level are: bridges,
breaks, extra devices, and missing devices. Suppose now that we have
a spot defect of size x. The layer sensitivity S(x) (defined as the
ratio of the total critical area to the total IC area) multiplied by
the probability of occurrence of the defect gives the probability of
failure of the layer. Semiconductor yield is the probability of
manufacturing devices without faults. A more realistic expresion for
modeling yield is:
Y(x,u) = ( 1 + c * A * D(x,u) * p(x,u)) ^ (-1/c)
where:
x = size of the defect
u = defect type
Y(x,u) = yield of the layer due to defects of size x and type u
c = spatial defect clustering parameter
A = Area of the IC
D(x,u) = Average defect density
p(x,u) = Probability of failure of the layer.
The IC yield is obtained by multiplying the yield of the individual
layers. Poisson statistics are not always suitable because it cannot
model the defect density variations within the wafer, and from wafer
to wafer. Thus, yield prediction is a bit more complicated than what
it looks like. It is a bit naive attempting to predict the IC yield
just by knowing its area.
===============================================================================
Jose Pineda.
Design Automation Section, Dept. of Electrical Engr.
Eindhoven University of Technology P.O. Box 513 5600 MB, Eindhoven The
Netherlands.
Tel (040)-473373
Email: jose@euteal.UUCP
(mcvax!hp4nl!eutrc3!euteal!jose)
===============================================================================