[comp.lsi] Glueing analog/digital simulators for mixed mode simulation

atul@parns.nsc.com (Atul) (06/16/89)

   
     Currently one popular approach to do mixed mode simulations is to
glue together analog/digital simulators by means of inter-process 
communication and some means of synchronization (eg, Viewlogic/Pspice,
Saber/Verilog etc).  Do fellow netters have any views on how well this
approach works ?

We have looked at the  PLI interface of Verilog for hooking up our proprietary
circuit simulator for mixed mode simulations and are awaiting further 
details on Verilink. However, we would be working under the constraint 
that we would not have the source code for the digital simulator. Would
this approach be feasible then ????

          Would appreciate any thoughts, ideas, pointers in this matter.

                       


-- 
*********************************************************************
     Atul P. Agarwal          |
National Semiconductor Corp., |  What is this life if full of care ?
   atul@parns.nsc.com         |  We have no time to stand and stare.

rdp@sda.UUCP (Russell dePina) (06/21/89)

In article <136@snappy.nsc.com> atul@snappy.UUCP (Atul) writes:
>
>   
>     Currently one popular approach to do mixed mode simulations is to
>glue together analog/digital simulators by means of inter-process 
>communication and some means of synchronization (eg, Viewlogic/Pspice,
>Saber/Verilog etc).  Do fellow netters have any views on how well this
>approach works ?
>
>We have looked at the  PLI interface of Verilog for hooking up our proprietary
>circuit simulator for mixed mode simulations and are awaiting further 
>details on Verilink. However, we would be working under the constraint 
>that we would not have the source code for the digital simulator. Would
>this approach be feasible then ????
>
>          Would appreciate any thoughts, ideas, pointers in this matter.
>
>                       
>
>
>-- 
>*********************************************************************
>     Atul P. Agarwal          |
>National Semiconductor Corp., |  What is this life if full of care ?
>   atul@parns.nsc.com         |  We have no time to stand and stare.

I have had some experience with using the Verilog PLI. Verilog uses the PLI to
interface with the Valid Network Realchip (NR II). It would be feasible to use
the PLI as an interface with another simulator, but getting the timing right is
really tricky. Some other neat things that you could try with the PLI is to
partition a design, and simulate parts of the design and use the PLI to
pass data and events to the other partitions. Some people have tried this
before, but I don't know what the results were. Anyway you asked for my $0.02
worth, there it is. Good Luck.

Russ de Pina
Cadence Design Systems
rdp@sda.uucp