wagner@irisa.fr (Charles Wagner) (05/27/91)
A 6-transistor RAM cell with split word lines can perform either two reads or one write. Time multiplexing a register array based on this cell with a two phase clocking method needs an extra phase ( recover phase ) generated by using a self-timed circuit. A row of dummy cells, hardwired to always contain a zero, is used to detect when a write has completed. I am looking for the design of such a self-timed circuit. If you can be of any help, please reply via email. Thanks.