speck@VLSI.CALTECH.EDU (Don Speck) (12/11/86)
There are times when one desires closely matched enhancement
thresholds - in sense amps, current mirrors, op amps, etc.
What sorts of things can one do in the layout to minimize
threshold differences? Obviously, the transistors should
be the same size (to minimize length and width dependence)
even under misalignment, and obviously they should have the
same number and kind of bends.
Do right-angle bends worsen the threshold variation? I try to
avoid them on general principle, but sometimes space is tight.
Will mirror-image or rotated transistors match as well as
transistors sharing a common orientation?
Does it help to make the transistors large, in hopes that the
threshold variations will average out? Do I need to draw
them long, or is it just the total gate area that matters?
Does the area/shape of the drain diffusion affect the threshold?
This tends to vary under misalignment.
Which polarity of transistor matches better, n or p, the
one built in the well, or the one built in the substrate?
Usually it's impossible to follow all the recommendations at
once, so which effects are significant and which aren't?
Don Speck speck@vlsi.caltech.edu {seismo,rutgers,ames}!cit-vax!speckclw@hprndlb.HP (Carl Wuebker) (12/26/86)
In matching, its a good idea to add some factor (.3, thru .5u to the
minimum gate dimensions so linewidth variations don't have as much effect
on your circuit. So, for example, if your design rules specify a 3.5u
long minimum gate length, go for a x/4.
In addition, we've found in our NMOS process that it makes sense
not to mirror the FETs -- this is because we connect to the gate with
a poly trace on one side (sometimes). A 'wash' which goes in the
gate direction can lengthen the gate on one of the mirrored pair and
shorten it on the other...
Good luck in your MOSIS project!
Thanks,
Carl Wuebker * {hpfcla|hplabs}!hprndlb!clw * Roseville Networks *