rpaul@mipon2.intel.com (Rick Paul (CMAD Guest)) (03/19/90)
I have a question about the misII tool included in the octtools 3.4 set. I am trying to synthesize a schematic that has a few levels of hierarchy in it. I have been able to simulate it with MUSA and I think that it is working properly, but I am having problems mapping it into a layout. I am using the MSU cell library for the mapping. The interface facet for each level of hierarchy was generated by a modified symgen, which extends the actions taken by the -c option to waranty that both interface and contents facets share formal terminals at the same location. After looking at the MUSA code, I figured that MUSA is smart enough to traverse the hierarchy and construct a proper model for it if you have the MODULE CELLTYPE property at each level of hierarchy, but misII is not as good about this and ignores anything that does not have the COMBINATIONAL CELLTYPE property. Is there a particular reason why misII does not read oct schematic the same way as MUSA ? Would it be wrong if I modified the misII code to read the hierarchy recursively ? Has it already been done ? What should I do ? Also, misII does not want to synthesize a DLATCH built out of gates, because it says that there is a loop. I know that the loop is there, but how can I tell misII that it is OK to go on. I thought about changing the CELLTYPE to SYNCHRONOUS, but then MUSA does not work on it. Would I be able to map transistor level schematic to a standard cell library ? What would it take ? Please reply to my regualr address: mzelada@cpoapr.intel.com Thanks in advance. ___________________________________________________________________________ | Name: Richard Paul | Tel: 602 554 2793, Fax: 961 3943 | | Dept: AME Methodology, SQA | E-mail: rpaul@mipon2.intel.com | | Group: Arizona Microcomputer Eng. | US-Mail: 5000 W. Chandler Blvd. | | Org: Intel Corporation, ASIC in the Desert, Chandler AZ, 85226 | ---------------------------------------------------------------------------
rpaul@mipon2.intel.com (Rick Paul (CMAD Guest)) (03/19/90)
I have a question about the MISII tool included in the octtools 3.4 set. I am trying to synthesize a schematic that has a few levels of hierarchy in it. I have been able to simulate it with MUSA and I think that it is working properly, but I am having problems mapping it into a layout. I am using the MSU cell library for the mapping. The interface facet for each level of hierarchy was generated by a modified symgen, which extends the actions taken by the -c option to warranty that both interface and contents facets share formal terminals at the same location. After looking at the MUSA code, I figured that MUSA is smart enough to traverse the hierarchy and construct a proper model for it if you have the MODULE CELLTYPE property at each level of hierarchy, but MISII is not as good about this and ignores anything that does not have the COMBINATIONAL CELLTYPE property. Is there a particular reason why MISII does not read oct schematic the same way as MUSA ? Would it be wrong if I modified the MISII code to read the hierarchy recursively ? Has it already been done ? What should I do ? Also, MISII does not want to synthesize a DLATCH built out of gates, because it says that there is a loop. I know that the loop is there, but how can I tell MISII that it is OK to go on. I thought about changing the CELLTYPE to SYNCHRONOUS, but then MUSA does not work on it. Would I be able to map transistor level schematic to a standard cell library ? What would it take ? Please reply to my regular address: mzelada@cpoapr.intel.com Thanks in advance. ___________________________________________________________________________ | Name: Richard Paul | Tel: 602 554 2793, Fax: 961 3943 | | Dept: AME Methodology, SQA | E-mail: rpaul@mipon2.intel.com | | Group: Arizona Microcomputer Eng. | US-Mail: 5000 W. Chandler Blvd. | | Org: Intel Corporation, ASIC in the Desert, Chandler AZ, 85226 | ---------------------------------------------------------------------------