johnm@btree.UUCP (10/23/87)
I'm interested in running a functional verification on the bipolar LSI design. Requirements for this simulator are: 1) Uses SPICE netlist with node names. 2) Able to simulate hierarchical design. 3) At least 10X speed improvement over SPICE, assuming that SPICE can even simulate it. 4) Able to detect incompatible voltage levels(i.e. high input voltage into ECL gate causing saturation). Does anyone know of such a simulator? Thanks in advance, John Muramatsu sdcsvax!btree!johnm
Jinfu_Jinfu_Chen@cup.portal.com.UUCP (11/30/87)
It depends on what hardware platform you have. From what I understand you aare atually looking for a logic simulator. I have used Mentor Grahpic's QuickSim for a LSI TTL/ECL design(SPICE can't even converge!). Although we have to develop our own models in order to detect different voltages hookup in ECL staggin logic. The speed is fast for sure but most of the features in SPICE are lost. The other alternative you might consider is to pertition your design into pieces and simulate them one by one. Then you may put all the timing information to a higher level logic design and use logic simulator(like QuickSIM) to check critical path, etc. Jinfu Chen -- Currently employedless