kerl@xenon.UUCP (Dan Kerl) (03/25/88)
I'm new to this group, I apologize if I missed any previous discussion on this topic. I am currently involved in a design that is going to silicon. A design issue that is currently worrying me is the implementation of flag synchronizers that are reliable at high clock rates (around 25 Mhz). I can't really afford package pins (and their associated propagation delay) necessary to place these flops externally - they need to be on the chip. Being burned by poor metastable characteristics in the past, I am somewhat leary of flipflops as implemented in gate-arrays. There also seems to be a total lack of useful information from ASIC vendors on this subject. Apart from suggestions of multiple-ranking, I have gotten nothing. I am interested in hearing about any experiences that any of you may have had concerning metastable effects in various synchronizer designs, as well as any suggestions on how to handle this phenomenon in the scope of the somewhat limited design options that the gate-array/standard-cell methodoligy offers. Also, I would appreciate any good references. You can send me email if you'd like, or just post the stuff. Thanks! - Dan ************************************************************************ * Daniel L. Kerl Intergraph Corp. M/S CR1105 * * UUCP: ihnp4!ingr!b11!xenon!kerl one Madison Industrial Park * * PHONE: 205-772-6118 Huntsville, Alabama 35807-4201 * ************************************************************************
ward@cfa.harvard.EDU (Steve Ward) (03/26/88)
In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes: > > I am currently involved in a design that is going to silicon. A design > issue that is currently worrying me is the implementation of flag > synchronizers that are reliable at high clock rates (around 25 Mhz). I > can't really afford package pins (and their associated propagation > delay) necessary to place these flops externally - they need to be on > the chip. > > I am interested in hearing about any experiences that any of you may > have had concerning metastable effects in various synchronizer designs, > Here is a circuit design of my own that works very well in HCT, HC, LS, and F logic families using the '74 D flip-flop. Since the D input is tied high it cannot transition during the mestastability (instability!) window which brackets the positive clock transition. This makes this design potentially metastable-immune. I say "potentially" because it depends on the "correct" internal design of the D flip-flop. So far, my use and testing shows exellent results. I cannot claim to have exhaustively tested the circuit to the extent that guarantees can be given for any application, but in my applications it has worked well. + | | O ------------ | P | + -----|D Q|----- | | | | clk -----|> | | | | _| | Q|O------------ OUTPUT | C | ------------ O | |______________________________________ | | | + | | | | | O | ------------- | | P | | + -----|D Q|----- | | | | | | | clk -----|> | | | | | | _| | | Q|O------------------------------ | C | ------------- O | | INPUT ----------------------- I prefer my synchronizer circuit shown here over the traditional multiple-stage shift-in (two or three stage shift-in) method. The obvious limitation is that the input signal toggle rate must be less than 1/2 the clock rate, and a symmetric clock period is assumed. Steven M. Ward ward@cfa.harvard.edu |
keithl@vice.TEK.COM (Keith Lofstrom) (03/27/88)
I work on A/D converters, where metastability in the comparators, as a result of comparators being "right on the edge", is a problem. Tek's oscilloscopes contain trigger circuits, which are essentially asynchronous state machines, where metastability results in "trigger jitter". In both cases, the answer is the same: 1) Make the bistable feedback circuit damn fast 2) Give the circuit as much time as possible to "make up its mind" Fancy biasing schemes don't often help much - they only change the conditions that cause metastability. The best scheme is usually a digital pipeline, which passes on unresolved signals, allowing later stages to make a decision. The decision made under these conditions is, of course, arbitrary, but nonetheless takes time to "create out of nothing". The bistable circuit inside a fast TTL IC may have time constants in the low hundreds of picoseconds, even if the part's gate delay is many nanoseconds. A MOS gate array flipflop is much slower, especially if the flipflop is loaded, so even best case there will be more metastability problems. If using such a flipflop, you should make sure the output is very lightly loaded, or use a cell with buffered outputs that are not part of the feedback loop. The metastability of the system will be on the order of exp[ -TIME/tau ] where TIME is the minimum resolution time, and tau is the bistable circuit's time constant. Find tau by playing with SPICE. Good Luck! -- Keith Lofstrom ...!tektronix!vice!keithl keithl@vice.TEK.COM MS 59-316, Tektronix, PO 500, Beaverton OR 97077 (503)-627-4052
upton@ole.UUCP (Mike Upton) (03/28/88)
some useful references: How to Avoid Synchronization Problems Peter Stoll, Intel VLSI DESIGN Nov-Dec 1982 On the Synchronization of a Microprocessor Chao et al. IBM IEEE Proceddings of the CICC 1986 pp447-450 The Behavior of Flip-Flops Used as Synchronizers... H. J. Veendrik IEEE Journal of Solid State Circuits Vol SC15 april 1980 pp 169-175 In general, Gate array and standard cell flip-flops have an inherent problem, they are designed to minimize area, and as a result suffer from meta-stability and setup-and hold problems. From my experience the best synchronizer element for an ASIC design would be the a 7474 flip-flop that is implemented as a "hard-macro", ie placed and routed as one unit. It is important that the flip-flop is implemented as cross-coupled nand or nor gates and the outputs from the ff are buffered. many ASIC flip-flops are implemented using master-slave latches, these are very dense but would not meet your requirements. Some other tricks can be played using parrelel synchronizers and a voting scheme, with different delay elements inserted before each synchronizer. This method does not suffer from the latency of a multiple cascaded flip-flop implementation. -- Michael Upton@Seattle Silicon (uucp: ...uw-beaver!tikal!ole!upton) /* Semi-conducting our business since 1983 */
phil@sci.UUCP (Phil Kaufman) (03/29/88)
In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes: > I am currently involved in a design that is going to silicon. A design > issue that is currently worrying me is the implementation of flag > synchronizers that are reliable at high clock rates (around 25 Mhz). I > can't really afford package pins (and their associated propagation > delay) necessary to place these flops externally - they need to be on > the chip. > > Being burned by poor metastable characteristics in the past, I am > somewhat leary of flipflops as implemented in gate-arrays. There also > seems to be a total lack of useful information from ASIC vendors on this > subject. Apart from suggestions of multiple-ranking, I have gotten > nothing. > > I am interested in hearing about any experiences that any of you may > have had concerning metastable effects in various synchronizer designs, > as well as any suggestions on how to handle this phenomenon in the scope > of the somewhat limited design options that the gate-array/standard-cell > methodoligy offers. Also, I would appreciate any good references. You > can send me email if you'd like, or just post the stuff. > You are absolutely right to be concerned and about the limits of most design systems and libraries. One solution you might consider is the Genesil silicon compiler from Silicon Compiler Systems. It includes special functions for synchronizers and hand-shake elements specifically to address these issues. (fodder for the length checker) phil
markf@amc.UUCP (Mark Freeman) (03/30/88)
A recent overview article on metastability is: Metastable Behavior in Digital Systems Linday Kleeman and Antonio Cantoni IEEE Design & Test of Computers V4 N6 (December 1987) In article <420@ole.UUCP>, upton@ole.UUCP (Mike Upton) writes: > Some other tricks can be played using parrelel synchronizers and > a voting scheme, with different delay elements inserted before > each synchronizer. This method does not suffer from the > latency of a multiple cascaded flip-flop implementation. In this article, the authors claim that voting schemes do not improve metastable behaviour over that of a single synchronizer. They reference another article of theirs, concerning this: Can Redundancy and Masking Improve the Performance of Synchronizers? ibid IEEE Transactions on Computers July 1986, pp. 643-646 I have not seen this article. -- Mark S. Freeman Applied Microsystems Corp. markf@amc
spp@zabriskie.uucp (Steve Pope) (03/30/88)
In article <18661@sci.UUCP> phil@sci.UUCP (Phil Kaufman) writes: >In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes: >> I am currently involved in a design that is going to silicon. A design >> issue that is currently worrying me is the implementation of flag >> synchronizers that are reliable at high clock rates (around 25 Mhz). I > >You are absolutely right to be concerned and about the limits of most >design systems and libraries. One solution you might consider is the >Genesil silicon compiler from Silicon Compiler Systems. It includes >special functions for synchronizers and hand-shake elements specifically >to address these issues. Phil, I'm sure SCI has great stuff in this area, but they're not the only ASIC operation that has a synchronizer macro. The real questions are: how is the synchronizer specified, what were the design principles, how is operation verified or simulated? And does it work at 25 MHz? (A 40 nsec synchronization interval is pretty short for CMOS.) steve