dlee@tut.cis.ohio-state.edu (Dik Lee) (04/01/89)
I like to find out what are the pros and cons of using wired logic (Wired-AND/OR) in vlsi design. Wired-logic can save a lot of logic gates, but I know it will also consume a larger amount of power, introduce more capacitance, need time to settle, etc. etc. It seems to me that it is not widely used in VLSI design. Is this true? I can't find any thorough discussion in the literature about wired logic in VLSI (I read an article on IEEE 893 FutureBus which uses wired logic, but the discussion is not for VLSI). I like to hear from people who have experience with wired-logic or know some references. I am interested in both nMOS and cMOS. - Dik Lee Dept. Computer and Information Science dlee@cis.ohio-state.edu The Ohio State University ..!osu-cis!cis.ohio-state.edu!dlee Columbus, OHIO 43210-1277 614-292-2568 -- Dept. Computer and Information Science dlee@tut.cis.ohio-state.edu The Ohio State University ..!osu-cis!cis.ohio-state.edu!dlee Columbus, OHIO 43210-1277 614-292-2568
bph@buengc.BU.EDU (Blair P. Houghton) (04/03/89)
In article <41352@tut.cis.ohio-state.edu> Dik Lee <dlee@cis.ohio-state.edu> writes: >I like to hear from people who have experience with wired-logic or >know some references. I am interested in both nMOS and cMOS. Putting pullups in parallel would render nMOS useless, unless there were seperate cell-designs for each level of parallelism (i.e., design with N cells in parallel, use versions of the N cells that have pullups N-times the length of a standalone cell's pullup; now, explain to the boss that the N-squared increase in pullup area and factor of max{N} cost increase in cell-library maintenance is somehow involved in "savings"...) Further, Wired-Or is anathema to CMOS. The first time the pullup of cell-A and the pulldown of cell-B simultaneously went "on", you'd be working in a (most probably unbalanced) ratioed region, wherupon Vout becomes (if you're lucky) about 2.5 volts. --Blair
flaig@Apple.COM (Charles Flaig) (04/04/89)
In article <2462@buengc.BU.EDU> bph@buengc.bu.edu (Blair P. Houghton) writes: >In article <41352@tut.cis.ohio-state.edu> Dik Lee <dlee@cis.ohio-state.edu> writes: >>I like to hear from people who have experience with wired-logic or >>know some references. I am interested in both nMOS and cMOS. > >Further, Wired-Or is anathema to CMOS. The first time the pullup of >cell-A and the pulldown of cell-B simultaneously went "on", you'd be >working in a (most probably unbalanced) ratioed region, wherupon Vout ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >becomes (if you're lucky) about 2.5 volts. > > --Blair I think this is the idea in any sort of wired-OR application. The general idea is that you have a weak common pull-up (pseudo NMOS) that can easily be over powered if any of the pull-downs go active. Having pull-up and pull-downs of equal strength produces a power-hungry majority circuit at best, not a wired-OR. Wired-OR is only anathema to CMOS in that it dissipates static power, as NMOS does, (and may or may not have a longer settling time) which the original poster mentioned. (There is a niggling change in noise immunity as well, but I won't worry about that here, since it shouldn't be a problem as long as you use fully restored signals on your inputs, don't have thousands of inputs, and have a reasonably stable power supply.) If you have an application with a large number of inputs to a gate, can afford the static power, have a desperate urge not to use the area required for active pull-ups, and don't have any gating signals available for a standard precharged solution, then wired-OR logic may be the way to go, even in CMOS. But you should know what you are doing (ie. don't do this on your first student project) and it should be avoided if there is a reasonable alternative. --Charles flaig@apple.com
brianr@tekig5.PEN.TEK.COM (Brian Rhodefer) (04/04/89)
I don't see why Wired-OR/AND logic would take any power whatever: it's passive. The `wired' node winds up with a lot of capacitance on it, though, so it won't switch as fast as an active gate. Occasionally, speed is of no concern, and a wired gate can be a win. A colleague used wire-ANDed gates to construct a multiplexer that effectively decoded his microprocessor peripheral's `read registers'. The host micro's memory read cycles were slow enough, relative to the speeds of the ASIC gates, that the wired-AND delivered adequate performance, at a lower chip real-estate cost than active circuitry would have required. Brian RHodefer !tektronix!tekig5!brianr
jps@wucs1.wustl.edu (James Sterbenz) (04/05/89)
In article <3971@tekig5.PEN.TEK.COM> brianr@tekig5.PEN.TEK.COM (Brian Rhodefer) writes: >A colleague used wire-ANDed gates to construct a multiplexer that >effectively decoded his microprocessor peripheral's `read registers'. >The host micro's memory read cycles were slow enough, relative to >the speeds of the ASIC gates, that the wired-AND delivered adequate >performance, at a lower chip real-estate cost than active circuitry >would have required. Assuming that this is a standard passive mux, this isn't really wire-ANDing; only the selected path is closed (two wires in CMOS, p and n halves of the xmit gate). This is more like dealing with tri-state, since logic levels are not being anded, one is being passed through with the others hi-Z. Now bipolar LSI is a different matter, but I doubt that the original poster was considering this. -- James Sterbenz Computer and Communications Research Center Washington University in St. Louis 314-726-4203 INTERNET: jps@wucs1.wustl.edu UUCP: wucs1!jps@uunet.uu.net