grout@sunspot.stars.flab.Fujitsu.JUNET (Steve Grout) (07/13/88)
This is Chapter 09 of a 1076-1987 VHDL test suite which was
translated from an 7.2 VHDL version test suite developed by
Intermetrics under funding by the DoD. These tests have been
verified todate mainly against a VHDL 'recognizer' so they may
yet have problems with VHDL semantics. They consist of two
classes of tests,
ERROR Tests: - names which start with 'e' should result in VHDL errors
at the spot where there is a comment about error being expected.
SIMPLE Tests: - names which start with 's' should analyze or compile cleanly.
These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to
make sure our various VHDL CAD tools work correctly.
Your comments and especially constructive criticism is urgently requested
via any way we can get it. All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.
Thanks for your support!
--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com
---- Cut Here and unpack ----
#!/bin/sh
#
# This is a 'shar' archive. Cut out everything above the line
# and unpack them with /bin/sh, i.e., using a command like:
# % sh < {the contents of this message after cutting}
#
#
echo "--------------------------------------------------"
echo "Starting to extract Chapter 09 of a 1076-1987 VHDL"
echo " translated DoD/Intermetrics test suite...."
echo "--------------------------------------------------"
echo x - e-09-1-0-0001a.vhdl
sed 's/^X//' >e-09-1-0-0001a.vhdl <<'*-*-END-of-e-09-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if a label appears at the end of the block statements, this label
X-- must be the same as the label at the beginning of the block statement.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
X B: block
X begin
X C : block
X begin
X process
X variable I : INTEGER;
X begin
X I := 1;
X end process;
X end block C;
X end block B1; -- ERROR NAME MUST MATCH THE ONE AT THE BEGINING OF THE BLOCK
Xend AB;
*-*-END-of-e-09-1-0-0001a.vhdl-*-*
echo x - e-09-1-0-0002a.vhdl
sed 's/^X//' >e-09-1-0-0002a.vhdl <<'*-*-END-of-e-09-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the guard condition must not be empty
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
X B : block ( ) -- ERROR: the guard condition must not be empty
X begin
X process
X begin
X return;
X end process;
X end block B;
Xend AB;
*-*-END-of-e-09-1-0-0002a.vhdl-*-*
echo x - e-09-1-0-0003a.vhdl
sed 's/^X//' >e-09-1-0-0003a.vhdl <<'*-*-END-of-e-09-1-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the guard condition, when present, must be a boolean expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic (A,B : INTEGER) ;
Xend E;
X
Xarchitecture AB of E is
Xbegin
XL_X_1: block ( A + B) -- ERROR: the guard condition must be boolean
X begin
X process
X begin
X return;
X end process;
X end block;
Xend AB;
X
Xarchitecture BB of E is
Xbegin
XL_X_2: block ( A * B) -- ERROR: the guard condition must be boolean
X begin
X process
X begin
X return;
X end process;
X end block;
Xend BB;
X
Xarchitecture CB of E is
Xbegin
XL_X_3: block ( A - B) -- ERROR: the guard condition must be boolean
X begin
X process
X begin
X return;
X end process;
X end block;
Xend CB;
X
Xarchitecture DB of E is
Xbegin
XL_X_4: block ( 'A') -- ERROR: the guard condition must be boolean
X begin
X process
X begin
X return;
X end process;
X end block;
Xend DB;
*-*-END-of-e-09-1-0-0003a.vhdl-*-*
echo x - e-09-1-0-0004a.vhdl
sed 's/^X//' >e-09-1-0-0004a.vhdl <<'*-*-END-of-e-09-1-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the implicitly declared signal GUARD must not be the target
X-- of a signal assignment statement nor passed to a formal port of mode "out" or
X-- "inout".
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X entity E is
X port (PT : boolean) ;
X end E;
X
X architecture AB of E is
X component C
X port (IO1 : inout BOOLEAN; O1 : out BOOLEAN);
X end component ;
Xbegin
XL_X_1: block (PT=FALSE)
Xbegin
X C_L1: C port map (IO1 => GUARD, O1 => GUARD);
X --ERROR: GUARD MUST NOT BE PASSED TO "OUT" OR "INOUT" FORMAL PORT
X process
X begin
X GUARD <= TRUE;
X --ERROR: GUARD MUST NOT BE TARGET OF SIGNAL ASSIGNMENT STATEMENT
X end process;
X end block;
X end AB;
X
*-*-END-of-e-09-1-0-0004a.vhdl-*-*
echo x - e-09-1-0-0005a.vhdl
sed 's/^X//' >e-09-1-0-0005a.vhdl <<'*-*-END-of-e-09-1-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that variable declarations are not permitted in a block statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (B:BIT) ;
Xend E;
X
Xarchitecture B1 of E is
X-- L_X_1: block
X variable V:BIT; --SEMANTICS ERROR: variables may not be declared in an
X -- architectural body
Xbegin
X process
X begin
X null;
X end process;
X-- end block;
Xend B1;
X
*-*-END-of-e-09-1-0-0005a.vhdl-*-*
echo x - e-09-1-0-0006a.vhdl
sed 's/^X//' >e-09-1-0-0006a.vhdl <<'*-*-END-of-e-09-1-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that port declarations (unless nested in component declarations),
X-- interface declarations, subprogram declarations, and
X-- body declarations are not permitted in a block statement.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B:BIT; C:out BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X port (A:BIT) ;
X--ERROR: port declaration not permitted in a body declaration
X-- L_X_1: block
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend B1;
X
Xarchitecture B2 of E1 is
X-- L_X_2: block
X entity E2 (B:BIT) is
X end E2;
X --ERROR: interface declaration not permitted inside body declaration
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend B2;
X
Xarchitecture B3 of E1 is
X-- L_X_3: block
X function F1 (A:BIT) return BIT is
X begin
X return ('0');
X end F1;
X -- Function declarations are permitted inside body declaration
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend B3;
X
Xarchitecture B4 of E1 is
X-- L_X_4: block
X procedure P1 is
X begin
X null;
X end;
X -- Procedure declarations are permitted inside body declaration
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend B4;
X
Xarchitecture B5 of E1 is
X-- L_X_5: block
X architecture B6 of E1 is
XL_X_6: block
X begin
X process
X begin
X null;
X end process;
X end block;
X end B6;
X --ERROR: body declarations not permitted inside body declaration
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend B5;
*-*-END-of-e-09-1-0-0006a.vhdl-*-*
echo x - e-09-1-0-0007a.vhdl
sed 's/^X//' >e-09-1-0-0007a.vhdl <<'*-*-END-of-e-09-1-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-1-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a label is required on each block statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
X block
X-- ERROR : missing block label
X begin
X process
X begin
X null;
X end process;
X end block;
Xend AB;
X
Xarchitecture AB of E is
Xbegin
X BB:block
X begin
X block
X -- ERROR : missing block label
X begin
X process
X begin
X null;
X end process;
X end block;
X end block;
Xend AB;
*-*-END-of-e-09-1-0-0007a.vhdl-*-*
echo x - e-09-2-0-0001a.vhdl
sed 's/^X//' >e-09-2-0-0001a.vhdl <<'*-*-END-of-e-09-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-2-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if a label appears at the end of a process statement, this label
X-- must also be given at the beginning of the process statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process
X begin
X return;
X end process P1; -- ERROR IF A NAME IS GIVEN IT MUST APPEAR AT THE BEGINNING
X-- end block; -- OF THE PROCESS DECLARATION
XEND BB;
*-*-END-of-e-09-2-0-0001a.vhdl-*-*
echo x - e-09-2-0-0002a.vhdl
sed 's/^X//' >e-09-2-0-0002a.vhdl <<'*-*-END-of-e-09-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: File: %P%
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Original file name: E-09-2-2-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if a sensitivity list is present it must not be empty.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process ( )
X -- ERROR THE SENSITIVITY LIST MUST NOT BE EMPTY
X begin
X return;
X end process;
X-- end block;
X end BB;
*-*-END-of-e-09-2-0-0002a.vhdl-*-*
echo x - e-09-2-0-0003a.vhdl
sed 's/^X//' >e-09-2-0-0003a.vhdl <<'*-*-END-of-e-09-2-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: File: %P%
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Original file name: E-09-2-2-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the sensitivity list when present must contain a static signal
X-- only
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X begin
X process('a') -- ERROR THE SENSITIVITY LIST MUST CONTAIN A STATIC SIGNAL
X begin
X return;
X end process;
X process (1) -- ERROR THE SENSITIVITY LIST MUST CONTAIN A STATIC SIGNAL
X begin
X return;
X end process;
X process( true)-- ERROR THE SENSITIVITY LIST MUST CONTAIN A STATIC SIGNAL
X begin
X return;
X end process;
X-- end block;
Xend BB;
*-*-END-of-e-09-2-0-0003a.vhdl-*-*
echo x - e-09-2-0-0004a.vhdl
sed 's/^X//' >e-09-2-0-0004a.vhdl <<'*-*-END-of-e-09-2-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-2-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that component declarations, signal declarations,
X-- and configuration specifications are not permitted in
X-- process statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E0 is
Xend E0;
X
X
Xentity E1 is
X port (B:BIT) ;
Xend E1;
X
X
Xarchitecture B1 of E1 is
X-- L_X_1: block
X begin
X process
X component C1 port (B:BIT); -- SEMANTICS ERROR: component declaration not
X end component ; -- permitted in process statement
X begin
X null;
X end process;
X-- end block;
Xend B1;
X
Xarchitecture B2 of E1 is
X-- L_X_2: block
X begin
X process
X signal S1:BIT; --SEMANTICS ERROR: signal declaration not
X -- permitted in process statement
X begin
X null;
X end process;
X-- end block;
Xend B2;
X
Xarchitecture B3 of E1 is
X-- L_X_3: block
X begin
X P1: process
X begin
X null;
X for P1 use -- SEMANTICS ERROR: configuration specification
X -- not permitted in process statement
X constant vi : integer := 1;
X end for;
X end process p1;
X-- end block L_X_3;
Xend B3;
*-*-END-of-e-09-2-0-0004a.vhdl-*-*
echo x - e-09-2-0-0005a.vhdl
sed 's/^X//' >e-09-2-0-0005a.vhdl <<'*-*-END-of-e-09-2-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-2-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that port declarations (unless nested in component declarations),
X-- interface declarations, function declarations, and
X-- body declarations are not permitted in process statement
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (B:BIT; C:out BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
X-- L_X_1: block
X begin
X process
X port map (X=>I1, Y => i2); -- SEMANTICS ERROR: interface declaration may not
X -- be in a process statement
X begin
X null;
X end process;
X-- end block;
Xend B1;
X
Xarchitecture B3 of E1 is
X-- L_X_2: block
X begin
X process
X function F return boolean is
X begin -- Function declaration may be used
X -- in a process statement.
X return true;
X end F;
X begin
X null;
X end process;
X-- end block;
Xend B3;
X
Xarchitecture B5 of E1 is
X-- L_X_4: block
X begin
X process
X begin
X architecture B6 of E1 is --SEMANTICS ERROR: body declarations may
X-- L_X_5: block -- not be nested
X begin
X process
X begin
X null;
X end process;
X-- end block;
X end B6;
X null;
X end process;
X-- end block;
Xend B5;
X
*-*-END-of-e-09-2-0-0005a.vhdl-*-*
echo x - e-09-5-0-0001a.vhdl
sed 's/^X//' >e-09-5-0-0001a.vhdl <<'*-*-END-of-e-09-5-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-4-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if both "guarded" and "transport" appear in the same concurrent
X-- signal assignment statement, "guarded" must precede "transport".
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port ( Pt : out Bit) ;
Xend E;
X
Xarchitecture Ab of E is
X-- L_X_1: block
X begin
X C1 : Pt <= transport guarded '1' ;
X-- ERROR TRANSPORT MUST NOT APPEAR BEFOR GUARDED
X-- end block;
Xend AB;
*-*-END-of-e-09-5-0-0001a.vhdl-*-*
echo x - e-09-5-1-0001a.vhdl
sed 's/^X//' >e-09-5-1-0001a.vhdl <<'*-*-END-of-e-09-5-1-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-4-1001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the characteristics of the waveforms and conditions must
X-- be such that the if statement in the equivalent process statement is
X-- legal statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: inout integer; PT2: inout character) ;
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1, S2 : boolean;
X begin
X
X PT <= 5 when S1 /= S2 else
X 6 when S1 > S2 else
X 7 when S1 + S2 else --ERROR conditions must be like those of
X -- an if statement in a process statement
X 9;
X PT2 <= 'A' when S1 = S2 --ERROR the waveform must be like if statement
X -- in an process statement.
X 'B' when S2 = S2 else
X 'C' ;
X
X-- end block;
Xend BB;
X
*-*-END-of-e-09-5-1-0001a.vhdl-*-*
echo x - e-09-5-1-0002a.vhdl
sed 's/^X//' >e-09-5-1-0002a.vhdl <<'*-*-END-of-e-09-5-1-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-4-1002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the final (or only) conditional waveform must not have a when
X-- clause.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:inout integer) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1, S2 : Boolean;
X begin
X PT <= 5 when S1 = S2 else
X 6 when S1 > S2 else
X 7 when S1 /= S2 else
X 9 when S1 < S2; -- ERROR : the final conditional waveform must
X -- not have a when clause.
X-- end block;
Xend AB;
*-*-END-of-e-09-5-1-0002a.vhdl-*-*
echo x - e-09-5-2-0001a.vhdl
sed 's/^X//' >e-09-5-2-0001a.vhdl <<'*-*-END-of-e-09-5-2-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-4-2001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that multiple selected waveforms must be separated by commas.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: inout boolean) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1,S2 : boolean;
X begin
X with PT select
X
X S1 <= true when false
X-- ERROR WAVEFROMS MUST BE SEPARATED BY COMMAS
X S2 <= true when true;
X-- end block;
Xend AB;
*-*-END-of-e-09-5-2-0001a.vhdl-*-*
echo x - e-09-5-2-0002a.vhdl
sed 's/^X//' >e-09-5-2-0002a.vhdl <<'*-*-END-of-e-09-5-2-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-4-2002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the characteristics of the the select expression ,the
X-- waveforms, and the choices must be such that the case statement in the
X-- equivalent process statement is a legal statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:inout integer ) ;
X end E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1,S2 : integer;
X begin
X with PT select
X S1 <= 1 when S2,
X 'A' when S1,
X -- ERROR LIKE A CASE STATEMENT,
X -- THE COMPARISION MUST BE OF THE SAME TYPE
X 2 when S2;
X-- end block;
Xend AB;
*-*-END-of-e-09-5-2-0002a.vhdl-*-*
echo x - e-09-6-0-0001a.vhdl
sed 's/^X//' >e-09-6-0-0001a.vhdl <<'*-*-END-of-e-09-6-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-5-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a label is required on each component instantiation
X-- statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- BB :block
X
X component C
X port(PT1:BOOLEAN;PT2:out BOOLEAN) ;
X end component ;
X signal S1,S2 : BOOLEAN;
X begin
X C port map (S1,PT2=>S2);
X -- ERROR : missing label on a component instantiation statement
X-- end block BB ;
Xend AB;
*-*-END-of-e-09-6-0-0001a.vhdl-*-*
echo x - e-09-6-0-0002a.vhdl
sed 's/^X//' >e-09-6-0-0002a.vhdl <<'*-*-END-of-e-09-6-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-5-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the component name (that is, the name of the kind of design entity
X-- being instantiated) in a component instantiation statement must have been
X-- declared in a component declaration.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- BB :block
X
X component C
X generic (G:INTEGER);
X port (PT1:BOOLEAN;PT2:out BOOLEAN) ;
X end component ;
X signal S1,S2 : BOOLEAN;
X begin
X C_0: C generic map (21) port map (PT1=>S2,PT2=>S1);
X C_1: D generic map (73) port map (TRUE,S1,PT2=>S2);
X -- ERROR : undeclared component name
X C_2: C1 generic map (-8) port map (S1,S2,S1,S2);
X -- ERROR : undeclared component name
X C_3: S1 generic map (0) port map (S2,PT2=>S1,PT1=>PT);
X -- ERROR : undeclared component name
X-- end block BB ;
Xend AB;
*-*-END-of-e-09-6-0-0002a.vhdl-*-*
echo x - e-09-7-0-0001a.vhdl
sed 's/^X//' >e-09-7-0-0001a.vhdl <<'*-*-END-of-e-09-7-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if a label appears at the end of the generate statement,
X-- this label must be the same as the label at the beginning of the
X-- generate statement.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X generic (IN_INT : INTEGER) ;
X port (X,Y: in BIT; COUT, COUT2: out BIT) ;
X
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : INTEGER);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
X
X begin
X GEN_1:
X for I in 1 to 1 generate
X C1: COMP_1 generic map (I) port map (X, COUT) ;
X end generate GEN_DIFF;
X --ERROR: IF A GENERATE STATEMENT HAS A LABEL AT THE END, IT MUST MATCH
X -- THE LABEL AT THE BEGINNING
X
X if IN_INT = 4 generate
X C2: COMP_1 generic map (IN_INT) port map (X, COUT2);
X end generate GEN_2;
X --ERROR: IF A GENERATE STATEMENT HAS A LABEL AT THE END, IT MUST MATCH
X -- THE LABEL AT THE BEGINNING
X
X S1 <= '0';
X-- end block;
Xend AB_1;
*-*-END-of-e-09-7-0-0001a.vhdl-*-*
echo x - e-09-7-0-0002a.vhdl
sed 's/^X//' >e-09-7-0-0002a.vhdl <<'*-*-END-of-e-09-7-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an "if" condition in a generate scheme must be of a boolean type.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT,COUT2: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port(A: in BIT; SOUT: out BIT) ;
X end component ;
X constant S1:BIT := '1';
X constant S2: INTEGER := 12;
X constant S3: INTEGER := 5;
X begin
X GEN_1:
X if S2 + S3 generate
X --ERROR: THE 'IF' CONDITION MUST BE BOOLEAN
X C1: COMP_1 generic map (hr) port map (X, COUT);
X end generate GEN_1;
X
X GEN_2:
X if S1**2 generate
X --ERROR: THE 'IF' CONDITION MUST BE BOOLEAN
X C2: COMP_1 generic map (3 min) port map (X, COUT2) ;
X end generate GEN_2;
X-- end block;
Xend AB_1;
*-*-END-of-e-09-7-0-0002a.vhdl-*-*
echo x - e-09-7-0-0003a.vhdl
sed 's/^X//' >e-09-7-0-0003a.vhdl <<'*-*-END-of-e-09-7-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a generate parameter is correctly typed from its discrete range
X-- (check using an equality operation with an operand of incompatible type in a
X-- nested "if" generation scheme).
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port (A: in BIT; SOUT: out BIT) ;
X end component ;
X type PHY_1 is range 1 to 2
X units
X single;
X double = 2 single;
X end units;
X type ARAY is array (1 to 10) of CHARACTER;
X type REAL_1 is range 1.0 to 9.0;
X type INT_1 is range 10 to 20;
X type ENUM_1 is (ONE,TWO,THREE);
X type REC_1 is record
X RE_1 : INTEGER;
X RE_2 : BIT;
X end record;
X signal S1 : BIT ;
X signal S2 : PHY_1;
X signal S3 : ARAY;
X signal S4 : REAL_1 ;
X signal S5 : INT_1 ;
X signal S6 : ENUM_1 ;
X signal S7 : REC_1;
X
Xbegin
X GEN_1:
X for I in 1 to 2 generate
XL_X_2: block
X begin
X process
X begin
X if I = S1 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X elsif I = S2 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X elsif I = S3 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X elsif I = S4 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X elsif I = S5 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X elsif I = S6 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X elsif I = S7 then
X --ERROR: THE GENERATE PARAMETER MUST BE OF THE TYPE OF ITS DISCRETE
X -- RANGE
X S1 <= '1';
X
X else
X S1 <= '0';
X end if;
X end process;
X end block;
X end generate GEN_1;
X-- end block;
Xend AB_1;
X
*-*-END-of-e-09-7-0-0003a.vhdl-*-*
echo x - e-09-7-0-0004a.vhdl
sed 's/^X//' >e-09-7-0-0004a.vhdl <<'*-*-END-of-e-09-7-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that no statement types other than valid concurrent statements
X-- such as component instantiation and generate
X-- statements, concurrent signal assignments, process, block,
X-- and concurrent assertion statements may occur in the sequence of
X-- statements of a generate statement. Check for concurrent signals assignment
X-- statements which are indistinguishable from signal assignment statements
X-- and concurrent assertion statements which are indistingushable from
X-- assertion statements. (Excluded are: variable assignment,
X-- procedure call, --NO - this is OK under 1076
X-- enable, disable,
X-- wait, loop, next, exit, if, case, null and return statements.)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
Xprocedure PROC_1 (Stmp : integer) ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X
Xprocedure PROC_1 (Stmp : integer) is
Xbegin
X null;
Xend PROC_1;
X
Xend P;
X
X-- with package P;
Xuse P.all;
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X signal S1:BIT ;
X signal S2:BOOLEAN ;
X
X begin
X for I in 1 to 1 generate
X S1 := '0';
X --ERROR: VARIABLE ASSIGNMENT STATEMENTS ARE NOT ALLOWED IN THE SEQUENCE
X -- OF STATEMENTS OF A GENERATE STATEMENT
X S2 <= FALSE;
X wait on S1, S2 ;
X -- ERROR: WAIT statement not allowed in sequence of statements
X -- of a generate statement
X null;
X -- ERROR: null statement not allowed in sequence of statements
X -- of a generate statement
X return ;
X -- ERROR: return statement not allowed in sequence of statements
X -- of a generate statement
X end generate;
X-- end block;
Xend AB_1;
X
Xarchitecture AB_2 of ENT_1 is
X-- L_X_2: block
X signal S1:BIT ;
X signal S2:BOOLEAN ;
X begin
X for I in 1 to 1 generate
X LOOP_1:
X for I := 1 to 1 loop
X --ERROR: LOOP STATEMENTS ARE NOT ALLOWED IN THE SEQUENCE
X -- OF STATEMENTS OF A GENERATE STATEMENT
X S1 <= '0';
X end loop LOOP_1;
X S2 <= FALSE;
X end generate;
X-- end block;
Xend AB_2;
X
Xarchitecture AB_3 of ENT_1 is
X-- L_X_3: block
X signal S1:BIT ;
X signal S2:BOOLEAN ;
X begin
X FOR I IN 1 to 3 generate
X next when I = 2;
X --ERROR: NEXT STATEMENTS ARE NOT ALLOWED IN THE SEQUENCE
X -- OF STATEMENTS OF A GENERATE STATEMENT
X
X S1 <= '1';
X end generate;
X-- end block;
Xend AB_3;
X
Xarchitecture AB_4 of ENT_1 is
X-- L_X_4: block
X signal S1:BIT ;
X signal S2:BOOLEAN ;
X begin
X for I in 1 to 1 generate
X exit when I = 2;
X -- ERROR: EXIT STATEMENT NOT ALLOWED IN SEQUENCE
X -- OF STATEMENTS OF A GENERATE STATEMENT
X
X S1 <= '0';
X S2 <= FALSE;
X end generate;
X-- end block;
Xend AB_4;
X
X
Xarchitecture AB_5 of ENT_1 is
X-- L_X_5: block
X signal S1:BIT ;
X signal S2:BOOLEAN ;
X begin
X for I in 1 to 1 generate
X PROC_1(S1);
X -- Procedure calls are allowed in sequence of statements
X -- of a generate statement
X if TRUE THEN
X S1 <= '0';
X else
X S2 <= FALSE;
X end if;
X -- ERROR: if statement not allowed in sequence of statements
X -- of a generate statement
X case BIT'('1') is
X when '1' => S1 <= '1';
X when '0' => S1 <= TRUE;
X end case;
X -- ERROR: case statement not allowed in sequence of statements
X -- of a generate statement
X
X end generate;
X-- end block;
Xend AB_5;
X
*-*-END-of-e-09-7-0-0004a.vhdl-*-*
echo x - e-09-7-0-0005a.vhdl
sed 's/^X//' >e-09-7-0-0005a.vhdl <<'*-*-END-of-e-09-7-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that non-discrete discrete ranges are not allowed in generate parameter
X-- specifications.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X generic (P_1 : TIME);
X port(A: in BIT; SOUT: out BIT) ;
X end component ;
X signal S1:BIT ;
Xbegin
X GEN_1:
X for GP_1 in 1.0 to 2.0 generate
X --ERROR: A GENERATE PARAMETER SPECIFICATION MUST HAVE A DISCRETE DISCRETE
X -- RANGE
X S1 <= '0';
X end generate GEN_1;
X-- end block;
Xend AB_1;
X
Xarchitecture AB_2 of ENT_1 is
X-- L_X_2: block
X component COMP_1
X port(A: in BIT; SOUT: out BIT);
X end component ;
X type PHY_1 is range 1 to 2
X units
X single;
X double = 2 single;
X end units;
X signal S1:BIT ;
X begin
X GEN_1:
X for GP_2 in single to double generate
X --ERROR: A GENERATE PARAMETER SPECIFICATION MUST HAVE A DISCRETE DISCRETE
X -- RANGE
X S1 <= '0';
X end generate GEN_1;
X-- end block;
Xend AB_2;
*-*-END-of-e-09-7-0-0005a.vhdl-*-*
echo x - e-09-7-0-0006a.vhdl
sed 's/^X//' >e-09-7-0-0006a.vhdl <<'*-*-END-of-e-09-7-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the lower and upper bounds of a discrete range in generate
X-- parameter specifications must be the same type.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- BLOCK_LABEL:block
X component COMP_1 port(A: in BIT; SOUT: out BIT);
X end component ;
X constant S1:BIT := '0';
X constant S2: INTEGER := 4;
X begin
X GEN1:
X for GP_1 in S1 to S2 generate
X --ERROR: THE LOWER AND UPPER BOUNDS OF A DISCRETE RANGE IN A
X -- GENERATE PARAMETER SPECIFICATION MUST BE THE SAME TYPE
X C_1: COMP_1 port map (X, COUT);
X end generate GEN1;
X-- end block;
Xend AB_1;
X
Xarchitecture AB_2 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port(A: in BIT; SOUT: out BIT);
X end component ;
X type ENUM_1 is (ONE,TWO,THREE);
X constant S2: INTEGER := 8;
X constant S3: ENUM_1 := TWO;
X begin
X GEN1:
X for GP_1 in S2 to S3 generate
X --ERROR: THE LOWER AND UPPER BOUNDS OF A DISCRETE RANGE IN A
X -- GENERATE PARAMETER SPECIFICATION MUST BE THE SAME TYPE
X C_1: COMP_1 port map (X, COUT);
X end generate GEN1;
X-- end block;
Xend AB_2;
X
Xarchitecture AB_3 of ENT_1 is
X-- L_X_2: block
X component COMP_1 port(A: in BIT; SOUT: out BIT);
X end component ;
X type SUB_1 is range 10 to 20;
X type SUB_2 is range 60 to 80;
X constant S2: SUB_1 := 15;
X constant S3: SUB_2 := 70;
Xbegin
X GEN1:
X for GP_1 in S2 to S3 generate
X --ERROR: THE LOWER AND UPPER BOUNDS OF A DISCRETE RANGE IN A
X -- GENERATE PARAMETER SPECIFICATION MUST BE THE SAME TYPE
X C_1: COMP_1 port map (X, COUT);
X end generate GEN1;
X-- end block;
Xend AB_3;
*-*-END-of-e-09-7-0-0006a.vhdl-*-*
echo x - e-09-7-0-0007a.vhdl
sed 's/^X//' >e-09-7-0-0007a.vhdl <<'*-*-END-of-e-09-7-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the lower and upper bounds in range specifications in generate
X-- parameter specifications must be generic expressions.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X generic (P_1: TIME := 3 ns) ;
X port (X,Y: in INTEGER; COUT,COUT2: out BIT_VECTOR) ;
X
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port(A: in INTEGER; SOUT: out BIT);
X end component ;
X signal S1:BIT ;
Xbegin
X GEN_1:
X if P_1 = 1 hr generate
X for GP1 in X to Y generate
X --ERROR: THE LOWER AND UPPER BOUNDS IN THE RANGE SPECIFICATION OF A
X -- GENERATE PARAMETER SPECIFICATION MUST BE GENERIC EXPRESSIONS
X C1: COMP_1 port map (X, COUT(GP1));
X end generate;
X end generate GEN_1;
X GEN_2:
X for GP2 in 1 to Y generate
X --ERROR: THE LOWER AND UPPER BOUNDS IN THE RANGE SPECIFICATION OF A
X -- GENERATE PARAMETER SPECIFICATION MUST BE GENERIC EXPRESSIONS
X S1 <= '1';
X end generate GEN_2;
X GEN_3:
X for GP3 in X to 3 generate
X --ERROR: THE LOWER AND UPPER BOUNDS IN THE RANGE SPECIFICATION OF A
X -- GENERATE PARAMETER SPECIFICATION MUST BE GENERIC EXPRESSIONS
X C2: COMP_1 port map (Y, COUT2(GP3));
X end generate GEN_3;
X-- end block;
Xend AB_1;
*-*-END-of-e-09-7-0-0007a.vhdl-*-*
echo x - e-09-7-0-0008a.vhdl
sed 's/^X//' >e-09-7-0-0008a.vhdl <<'*-*-END-of-e-09-7-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the "if" condition must be a generic expression.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; COUT1,COUT2,COUT3: out BIT_VECTOR) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port (A: in BIT; SOUT: out BIT_VECTOR);
X end component ;
X signal S1:BIT ;
X signal FUN_1 : INTEGER;
X begin
X GEN_1:
X if FUN_1 > 3 generate
X --ERROR: THE 'IF' CONDITION OF A GENERATE STATEMENT MUST BE A
X -- GENERIC EXPRESSION
X C1: COMP_1 port map (X, COUT1);
X end generate GEN_1;
X GEN_2:
X for I in 1 to 3 generate
X if I = FUN_1 generate
X --ERROR: THE 'IF' CONDITION OF A GENERATE STATEMENT MUST BE A
X -- GENERIC EXPRESSION
X C2: COMP_1 port map (X, COUT2);
X end generate;
X C3: COMP_1 port map ( Y, COUT3);
X end generate GEN_2;
X S1 <= '0' after 2 ns;
X-- end block;
Xend AB_1;
*-*-END-of-e-09-7-0-0008a.vhdl-*-*
echo x - e-09-7-0-0009a.vhdl
sed 's/^X//' >e-09-7-0-0009a.vhdl <<'*-*-END-of-e-09-7-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the generate parameter may not be the target of an assignment
X-- statement.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X generic (P_1: TIME := 3 ns) ;
X port (X,Y: in BIT; COUT1,COUT2: out BIT_VECTOR) ;
X
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port(A: in BIT; SOUT: out BIT_VECTOR);
X end component ;
X signal S1:BIT ;
X begin
X GEN_1:
X if BIT ' ('0') = '0' generate
X for GP1 in 1 to 3 generate
X C1: COMP_1 port map (X, COUT1);
X GP1 <= 2 after 2 ns;
X --ERROR: THE GENERATE PARAMETER CANNOT BE THE TARGET
X -- OF AN ASSIGNMENt
X end generate;
X end generate GEN_1;
X GEN_2:
X for GP2 in 1 to 3 generate
X if P_1 < 12 ns generate
X GP2 <= 2;
X --ERROR: THE GENERATE PARAMETER CANNOT BE THE TARGET
X -- OF AN ASSIGNMENT
X end generate;
X S1 <= '1';
X end generate GEN_2;
X GEN_3:
X for GP3 in 1 to 3 generate
X C2: COMP_1 port map (Y, COUT2);
X GP3 <= 1 after 2 ns, 2 after 4 ns, 3 after 6 ns;
X --ERROR: THE GENERATE PARAMETER CANNOT BE THE TARGET
X -- OF AN ASSIGNMENT
X end generate GEN_3;
X-- end block;
Xend AB_1;
X
*-*-END-of-e-09-7-0-0009a.vhdl-*-*
echo x - e-09-7-0-0010a.vhdl
sed 's/^X//' >e-09-7-0-0010a.vhdl <<'*-*-END-of-e-09-7-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-6-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the generate parameter may not be used as an "out", "buffer",
X-- "linkage", or "inout" actual port in a component instantiation statement.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X generic (P_1: TIME := 3 ns) ;
X port (X,Y: in BIT; COUT: out BIT_VECTOR) ;
X
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port(A: in BIT; B: inout INTEGER; SOUT: out BIT_VECTOR;
X D: linkage BIT; E : buffer INTEGER);
X end component ;
X signal S1, S43, S13, S23 :BIT ;
X signal S22, S32, S42, S14, S24, S34 : INTEGER ;
X begin
X GEN_1:
X if BIT ' ('0') = '0' generate
X for GP1 in 1 to 3 generate
X C1: COMP_1 port map (X, GP1, COUT, S13, S14);
X --ERROR: THE GENERATE PARAMETER MAY NOT BE USED AS AN
X -- 'INOUT' ACTUAL PORT IN A COMPONENT INSTANTIATION STATEMENT
X end generate;
X end generate GEN_1;
X GEN_2:
X for GP2 in 1 to 3 generate
X if P_1 < 12 ns generate
X C2: COMP_1 port map (X, S22, GP2, S23, S24);
X --ERROR: THE GENERATE PARAMETER MAY NOT BE USED AS AN 'OUT'
X -- ACTUAL PORT IN A COMPONENT INSTANTIATION STATEMENT
X end generate;
X S1 <= '1';
X end generate GEN_2;
X GEN_3:
X for GP3 in 1 to 3 generate
X if P_1 < 12 ns generate
X C3: COMP_1 port map (X, S32, COUT, GP3, S34);
X --ERROR: THE GENERATE PARAMETER MAY NOT BE USED AS A 'LINKAGE'
X -- ACTUAL PORT IN A COMPONENT INSTANTIATION STATEMENT
X end generate;
X S1 <= '1';
X end generate GEN_3;
X GEN_4:
X for GP4 in 1 to 3 generate
X if P_1 < 12 ns generate
X C4: COMP_1 port map (X, S42, COUT, S43, GP4);
X --ERROR: THE GENERATE PARAMETER MAY NOT BE USED AS A 'BUFFER'
X -- ACTUAL PORT IN A COMPONENT INSTANTIATION STATEMENT
X end generate;
X S1 <= '1';
X end generate GEN_4;
X-- end block;
Xend AB_1;
X
X
*-*-END-of-e-09-7-0-0010a.vhdl-*-*
echo x - s-09-0-0-0001a.vhdl
sed 's/^X//' >s-09-0-0-0001a.vhdl <<'*-*-END-of-s-09-0-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that concurrent signal assignment, concurrent assertion, generate,
X-- and component instantiation statements are permitted in a set of
X-- statements. Check that concurrent assertion statements which are
X-- indisguishable from assertion statements and concurrent signal assignment
X-- statements which are indistinguishable from signal assignment statements are
X-- also permitted.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port ( Pt : in BOOLEAN;
X PTO : out BIT) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1, S2 : Integer;
X signal S : INTEGER ;
X
X component FO port (F1,F2,F3 : INTEGER) ;
X end component ;
X
X begin
X -- concurrent signal statement
X S <= transport 5;
X
X -- concurrent assertion statement
X assert ( not PT)
X report " dead wire "
X severity WARNING;
X
X -- generate
X for I in 1 to 5 generate
XL_X_2: block
X signal S3 : Bit;
X begin
X S2 <= transport 1;
X end block;
X end generate;
X
X -- component instatiation
X Ls : FO port map (S1,S2,S);
X-- end block;
Xend AB;
*-*-END-of-s-09-0-0-0001a.vhdl-*-*
echo x - s-09-0-0-0001b.vhdl
sed 's/^X//' >s-09-0-0-0001b.vhdl <<'*-*-END-of-s-09-0-0-0001b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-09-2-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a set of statements must not be empty. Check block and
X-- generate statements.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X-- end block;
X -- BLOCK MAY BE EMPTY
Xend AB;
X
X
Xarchitecture BB of E is
X-- L_X_2: block
X begin
X if True generate
X end generate;
X -- GENERATE STATEMENT MAY BE EMPTY
X-- end block;
Xend BB;
*-*-END-of-s-09-0-0-0001b.vhdl-*-*
echo x - s-09-1-0-0001a.vhdl
sed 's/^X//' >s-09-1-0-0001a.vhdl <<'*-*-END-of-s-09-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that repetition of the block label at the end of the block statement
X-- is optional.
X-- JB (DB 7/18/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
Xbegin
XC : block
X begin
X D : block
X begin
X process
X begin
X return;
X end process;
X end block D;
X end block;
Xend BB;
*-*-END-of-s-09-1-0-0001a.vhdl-*-*
echo x - s-09-1-0-0002a.vhdl
sed 's/^X//' >s-09-1-0-0002a.vhdl <<'*-*-END-of-s-09-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the guard condition is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E ;
X
Xarchitecture AE of E is
Xbegin
XB1:block --<< no guard condition here
Xbegin
X process
X begin
X null ;
X end process ;
Xend block ;
Xend AE ;
*-*-END-of-s-09-1-0-0002a.vhdl-*-*
echo x - s-09-1-0-0003a.vhdl
sed 's/^X//' >s-09-1-0-0003a.vhdl <<'*-*-END-of-s-09-1-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that there is an implicit declaration for signal GUARD of type
X-- boolean at the beginning of the block declarative part. Check when
X-- there is no guard condition.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
XL_X_1: block
X begin
X assert GUARD <= false;
X end block;
Xend AB;
*-*-END-of-s-09-1-0-0003a.vhdl-*-*
echo x - s-09-1-0-0004a.vhdl
sed 's/^X//' >s-09-1-0-0004a.vhdl <<'*-*-END-of-s-09-1-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the implicity declared signal GUARD may be associated to a formal
X-- port of mode "in", "buffer", or "linkage".
X-- JB (DB 7/18/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (PT : buffer BOOLEAN; PT1 : linkage BOOLEAN; PT2 : BOOLEAN) ;
Xend E1;
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
XL_X_1: block
X component C1 port ( BUF1 : buffer BOOLEAN;
X LINK1 : linkage BOOLEAN;
X IN1 : BOOLEAN );
X end component ;
X for AL : C1
X use
X entity E1
X port map (PT => BUF1, PT1 => LINK1, PT2 => IN1)
X-- architecture(open); -- 7.2
X-- end for; -- 7.2
X ;
X signal S1, S2, S3 : BOOLEAN ;
X begin
X AL : C1 port map ( BUF1 => S1, LINK1 => S2, IN1 => GUARD);
X end block;
Xend AB;
*-*-END-of-s-09-1-0-0004a.vhdl-*-*
echo x - s-09-1-0-0005a.vhdl
sed 's/^X//' >s-09-1-0-0005a.vhdl <<'*-*-END-of-s-09-1-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the implicitly declared signal GUARD may be explicitly
X-- passed as an actual signal in a component instantiation.
X-- JB (DB 7/18/85,9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT: BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X component COMP_1 port (W,X : BOOLEAN);
X end component ;
X signal S3 : BOOLEAN;
X begin
X C_1: COMP_1 port map (W => GUARD, X => S3);
X-- end block;
Xend AB;
*-*-END-of-s-09-1-0-0005a.vhdl-*-*
echo x - s-09-1-0-0006a.vhdl
sed 's/^X//' >s-09-1-0-0006a.vhdl <<'*-*-END-of-s-09-1-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that configuration specifications, and type, subtype, signal,
X-- alias, component, and attribute declarations are permitted in a block
X-- statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EMP is
X port ( S_in : in Bit; S_out : out Bit) ;
Xend EMP;
X
Xentity E1 is
X port (B:BIT) ;
Xend E1;
X
Xarchitecture B1 of E1 is
Xbegin
XL_X_1: block
X component C1 port(A:BIT;B:out BIT);
X end component ;
X type T1 is ('0','1');
X subtype T2 is INTEGER range 0 to 7;
X signal S1:REAL;
X alias S1_too : REAL is S1;
X-- attribute ATTR of signal is T1; -- 7.2
X attribute ATTR of ALL : signal is T1; -- 1076
X for all : C1
X use
X entity EMP
X port map( S_in => A, S_out => B)
X-- architecture ( open);
X-- end for;
X ;
X begin
X process
X begin
X null;
X end process;
X end block;
Xend B1;
X
X
Xentity C1 is
X port (A:BIT; B:out BIT) ;
Xend C1;
X
*-*-END-of-s-09-1-0-0006a.vhdl-*-*
echo x - s-09-1-0-0007a.vhdl
sed 's/^X//' >s-09-1-0-0007a.vhdl <<'*-*-END-of-s-09-1-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-1-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that formal port lists are optional for block statements.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
Xbegin
X BB:block
X -- optional formal port list is not specified
X begin
X process
X begin
X null;
X end process;
X end block;
Xend AB;
*-*-END-of-s-09-1-0-0007a.vhdl-*-*
echo x - s-09-2-0-0001a.vhdl
sed 's/^X//' >s-09-2-0-0001a.vhdl <<'*-*-END-of-s-09-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-2-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the process label is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X begin
X P1: process
X begin
X null;
X end process P1;
X-- end block;
Xend AB;
X
Xarchitecture BB of E is
X-- L_X_2: block
X begin
X process
X begin
X null;
X end process ;
X-- end block;
Xend BB;
X
*-*-END-of-s-09-2-0-0001a.vhdl-*-*
echo x - s-09-2-0-0002a.vhdl
sed 's/^X//' >s-09-2-0-0002a.vhdl <<'*-*-END-of-s-09-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-2-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the sensitivity list is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (PT:boolean) ;
Xend E1;
X
Xarchitecture AB of E1 is
X-- L_X_1: block
X begin
X process (PT)
X begin
X null;
X end process;
X-- end block;
Xend AB;
X
Xarchitecture BB of E1 is
X-- L_X_2: block
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend BB;
X
X
*-*-END-of-s-09-2-0-0002a.vhdl-*-*
echo x - s-09-2-0-0003a.vhdl
sed 's/^X//' >s-09-2-0-0003a.vhdl <<'*-*-END-of-s-09-2-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-2-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that type, subtype, variable, and attribute declarations are permitted
X-- in a process statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
Xend E1;
X
Xarchitecture AB of E1 is
X-- L_X_1: block
X begin
X process
X type T1 is range 1 to 100;
X subtype T2 is T1 range 1 to 50;
X variable V1 : T2;
X-- attribute A1 of variable is BOOLEAN ; -- 7.2
X-- for A1 of variable use true; -- 7.2
X attribute A1 : BOOLEAN ;
X attribute A1 of E1 : variable is true;
X begin
X null;
X end process;
X-- end block;
Xend AB;
*-*-END-of-s-09-2-0-0003a.vhdl-*-*
echo x - s-09-4-0-0001a.vhdl
sed 's/^X//' >s-09-4-0-0001a.vhdl <<'*-*-END-of-s-09-4-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-3-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the assertion label is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture BB of E is
X-- L_X_1: block
X signal S1, S2: boolean;
Xbegin
X assert S1 <= true report "bad s1" severity warning;
X A1 : assert S2 <= false;
X-- end block;
Xend BB;
*-*-END-of-s-09-4-0-0001a.vhdl-*-*
echo x - s-09-4-0-0002a.vhdl
sed 's/^X//' >s-09-4-0-0002a.vhdl <<'*-*-END-of-s-09-4-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-3-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the implicitly declared signal GUARD may be referenced in the
X-- the boolean expression of a concurrent assertion statment.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (S1 : in boolean) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block (S1)
X begin
X assert S1 report "bad S1" ;
X-- end block;
Xend AB;
*-*-END-of-s-09-4-0-0002a.vhdl-*-*
echo x - s-09-5-0-0001a.vhdl
sed 's/^X//' >s-09-5-0-0001a.vhdl <<'*-*-END-of-s-09-5-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-4-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the reserved word MEMORIED is optional whether or not the
X-- reserved word TRANSPORT appears.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port ( PT : out boolean) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1,S2 : boolean;
X begin
X C2 : Pt <= transport False ;
X-- end block;
Xend AB;
*-*-END-of-s-09-5-0-0001a.vhdl-*-*
echo x - s-09-5-0-0002a.vhdl
sed 's/^X//' >s-09-5-0-0002a.vhdl <<'*-*-END-of-s-09-5-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-4-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the reserved word TRANSPORT is optional whether or not the
X-- reserved word MEMORIED appears.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT : out boolean) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal S1 : Boolean;
X begin
X C2 : Pt <= guarded S1 <= False ;
X-- end block;
Xend AB;
*-*-END-of-s-09-5-0-0002a.vhdl-*-*
echo x - s-09-5-0-0003a.vhdl
sed 's/^X//' >s-09-5-0-0003a.vhdl <<'*-*-END-of-s-09-5-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-4-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that "memoried" and "transport" may both appear in the same
X-- concurrent signal assignment.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E (PT: out boolean) is
Xend E;
X
Xarchitecture AB of E is
XL_X_1: block
X signal S1, S2 : boolean;
X begin
X C1 : Pt <= memoried transport S1 <= false ;
X end block;
Xend AB;
*-*-END-of-s-09-5-0-0003a.vhdl-*-*
echo x - s-09-6-0-0001a.vhdl
sed 's/^X//' >s-09-6-0-0001a.vhdl <<'*-*-END-of-s-09-6-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-5-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the same simple name may be used on more than one component
X-- instantiation statements in an block statement.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X component C
X port(X:IN REAL);
X end component ;
X component D
X generic (X:INTEGER);
X port (W:INOUT REAL);
X end component ;
X signal V1 : INTEGER;
X signal Y,Z : REAL;
X signal S1 : REAL;
X begin
X L1: C port map (S1);
X L2: D generic map (10) port map (Z) ;
X L3: for I in INTEGER generate
X L4: C port map (Z);
X L5: D generic map (4) port map (Y) ;
X end generate L3;
X-- end block;
Xend AB;
*-*-END-of-s-09-6-0-0001a.vhdl-*-*
echo x - s-09-6-0-0002a.vhdl
sed 's/^X//' >s-09-6-0-0002a.vhdl <<'*-*-END-of-s-09-6-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-5-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the port portion of a component instantiation statement is
X-- optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X component C generic (X:IN REAL);
X end component ;
X component D
X generic (A:INTEGER);
X port(W:INOUT REAL);
X end component ;
X signal V1 : INTEGER;
X constant Z : REAL := 3.1415;
X signal Z1 : REAL;
X signal Z2 : REAL;
X begin
X L1: C generic map (Z);
X -- port portion of component instantiation is optional.
X C_2: D generic map (10) port map (Z1) ;
X L3: for I in INTEGER generate
X C_1: C generic map (Z) ;
X -- port portion of component instantiation is optional.
X L4: C generic map (10.2);
X -- port portion of component instantiation is optional.
X end generate L3;
X-- end block;
Xend AB;
*-*-END-of-s-09-6-0-0002a.vhdl-*-*
echo x - s-09-6-0-0003a.vhdl
sed 's/^X//' >s-09-6-0-0003a.vhdl <<'*-*-END-of-s-09-6-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-5-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the generic portion of a component instantiation
X-- statement is optional.
X-- Note: When a component declaration has a generic parameter portion it may
X-- still be optional in the component instantiation if there is a default
X-- value in the original interface declaration. However it cannot appear in
X-- instantiation if it is not in both the component and interface declarations.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X component C port(X:IN REAL);
X end component ;
X component D
X generic (A:INTEGER);
X port(W:INOUT REAL) ;
X end component ;
X signal V1 : INTEGER;
X signal Z : REAL;
X signal Z1 : REAL;
X signal Z2 : REAL;
X begin
X L1: C port map (Z);
X C_2: D generic map (10) port map (Z1) ;
X L3: for I in INTEGER generate
X C_1: C port map (Z) ;
X L4: C port map (Z2);
X end generate L3;
X-- end block;
Xend AB;
*-*-END-of-s-09-6-0-0003a.vhdl-*-*
echo x - s-09-7-0-0001a.vhdl
sed 's/^X//' >s-09-7-0-0001a.vhdl <<'*-*-END-of-s-09-7-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all discrete types may be used as generate parameters. Check for
X-- enumeration (user-defined, predefined( character, bit, boolean) and integer
X-- types.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; Z: inout BIT_VECTOR; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1 port(A: in BIT; SOUT: out BIT);
X end component ;
X type COLOR is (RED, ORANGE, YELLOW, GREEN);
X type ARRAY_1 is array (RED to GREEN) of BIT;
X type NAME is ('V', 'H', 'D', 'L');
X type ARRAY_2 is array (NAME range 'V' to 'L') of BIT;
X type FOO is ('0', '1');
X signal S1:BIT ;
X signal S2: ARRAY_1;
X signal S3: ARRAY_2;
X signal S4: FOO;
X signal S5: BIT ;
X signal S6: BIT ;
X begin
X GEN_1:
X for GP1 in ORANGE to GREEN generate
X S1 <= S2(GP1);
X end generate GEN_1;
X
X GEN_2:
X for GP2 in NAME ' ('V') to NAME ' ('H') generate
X C1: COMP_1 port map (X, S5);
X S3(GP2) <= S1;
X end generate GEN_2;
X
X GEN_3:
X for GP3 in FOO ' ('0') to FOO ' ('1') generate
X S2(RED) <= S1 ;
X S4 <= GP3;
X end generate GEN_3;
X
X GEN_4:
X for GP4 in FALSE to TRUE generate
X C_1: COMP_1 port map (Y, S6);
X end generate GEN_4;
X
X GEN_5:
X for GP5 in 1 to 3 generate
X Z(GP5) <= S1 ;
X end generate GEN_5;
X-- end block;
Xend AB_1;
*-*-END-of-s-09-7-0-0001a.vhdl-*-*
echo x - s-09-7-0-0002a.vhdl
sed 's/^X//' >s-09-7-0-0002a.vhdl <<'*-*-END-of-s-09-7-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that component instantiations and generate, concurrent signal
X-- assignment, concurrent assertion, block and proess statements are all
X-- permitted in the set of statement of a generate statement. Check
X-- for concurrent signal assignment statements which are indistingushable from
X-- signal assignment statements and concurrent assertion statements which are
X-- indistingushable from assertion statements.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT_VECTOR; COUT: out BIT_VECTOR) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X constant TTTT : BOOLEAN := TRUE;
X component COMP_1 port(A: in BIT; SOUT: out BIT);
X end component ;
X signal S1:BIT ;
X signal S2: POSITIVE ;
X signal S3: BOOLEAN ;
X signal COUT_tmp : BIT_VECTOR (1 to 10) ;
X begin
X GEN_1:
X for I in 1 to 3 generate
XL_X_2: block
X begin
X process
X begin
X if S1 = '1' then
X null ;
X end if;
X COUT(I) <= S1;
X end process;
X C1: COMP_1 port map (X(I), COUT_tmp(I+1));
X end block;
X end generate GEN_1;
X
X GEN_2:
X if TTTT generate
XL_X_3: block
X begin
X GEN_2_1:
X for I in 1 to 2 generate
XL_X_4: block
X begin
X process
X constant C1 : Integer := 0 ;
X constant C2 : BIT := '0' ;
X begin
X case S3 is
X when (
X (C1 < 5)
X and (C2 = '1')
X ) => S2 <= S2 + 1;
X when others => S1 <= '1';
X end case;
X end process;
X end block;
X end generate GEN_2_1;
X end block;
X end generate GEN_2;
X-- end block;
Xend AB_1;
*-*-END-of-s-09-7-0-0002a.vhdl-*-*
echo x - s-09-7-0-0003a.vhdl
sed 's/^X//' >s-09-7-0-0003a.vhdl <<'*-*-END-of-s-09-7-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that generic expressions are permitted in lower and upper bounds in
X-- range specifications in generate parameter specifications.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic (G1:INTEGER;G2,G3:BIT) ;
X port (PT:inout BOOLEAN) ;
X
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X constant C : INTEGER := 0 ;
X signal S1 : BOOLEAN ;
X signal S2 : BOOLEAN ;
X signal S3 : BOOLEAN ;
X begin
X L1: for GP1 in G2 to G3 generate
X PT <= TRUE;
X end generate L1;
X for GP2 in C to 5 generate
X S1 <= TRUE;
X end generate;
X L2: for GP3 in BOOLEAN range TRUE to FALSE generate
X S2 <= TRUE;
X end generate L2;
X for GP4 in 0 to 3*abs G1+10 generate
X S3 <= TRUE;
X end generate;
X-- end block;
Xend AB;
*-*-END-of-s-09-7-0-0003a.vhdl-*-*
echo x - s-09-7-0-0004a.vhdl
sed 's/^X//' >s-09-7-0-0004a.vhdl <<'*-*-END-of-s-09-7-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the "if" condition may be a generic expression.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic (G1:INTEGER;G2,G3:BIT) ;
X port (PT:inout BOOLEAN) ;
X
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal PT1 : BOOLEAN ;
X signal PT2 : BOOLEAN ;
X signal PT3 : BOOLEAN ;
X begin
X if G2/=G3 and G2<not G3 generate
X PT <= TRUE;
X end generate;
X L1: if not(abs G1>23) generate
X PT1 <= TRUE;
X end generate L1;
X if 'C'<CHARACTER'PRED('C') generate
X PT2 <= TRUE;
X end generate;
X L2: if G2='1' generate
X PT3 <= TRUE;
X end generate L2;
X-- end block;
Xend AB;
*-*-END-of-s-09-7-0-0004a.vhdl-*-*
echo x - s-09-7-0-0005a.vhdl
sed 's/^X//' >s-09-7-0-0005a.vhdl <<'*-*-END-of-s-09-7-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a null discrete range is permitted.
X-- Check that the discrete range may be specified as LOW to HIGH and as
X-- HIGH to LOW, LOW downto HIGH, or HIGH downto LOW.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X generic (G1:INTEGER;G2,G3:BIT) ;
X port (PT:inout BOOLEAN) ;
X
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X signal PT1 : BOOLEAN ;
X signal PT2 : BOOLEAN ;
X signal PT3 : BOOLEAN ;
X signal PT4 : BOOLEAN ;
X begin
X for GP in G2 to G3 generate
X PT <= TRUE;
X end generate;
X L1: for GP1 in 'C' downto 'Z' generate
X PT1 <= TRUE;
X end generate L1;
X for GP2 in BIT range '1' downto '1' generate
X PT2 <= TRUE;
X end generate;
X L2: for GP3 in 0 to 3*abs G1+10 generate
X PT3 <= TRUE;
X end generate L2;
X for GP4 in 0 to -1 generate
X PT4 <= TRUE;
X end generate;
X-- end block;
Xend AB;
*-*-END-of-s-09-7-0-0005a.vhdl-*-*
echo x - s-09-7-0-0006a.vhdl
sed 's/^X//' >s-09-7-0-0006a.vhdl <<'*-*-END-of-s-09-7-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the generate parameter may be used an "in" or as a "linkage"
X-- actual port in a component instantiation statement.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; Z: linkage INTEGER; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X port(A: in BIT; B: linkage INTEGER; SOUT: out BIT);
X end component ;
X signal S1: BIT ;
X signal S2: INTEGER ;
X begin
X
X GEN_1:
X for GP1 in 1 to 5 generate
XL_X_2: block
X begin
X C1: COMP_1 port map (X, S2, COUT);
X end block;
X end generate GEN_1;
X
X GEN_2:
X for GP2 in BIT range '0' to '1' generate
XL_X_3: block
X begin
X C2: COMP_1 port map (S1, Z, S1);
X end block;
X end generate GEN_2;
X-- end block;
Xend AB_1;
*-*-END-of-s-09-7-0-0006a.vhdl-*-*
echo x - s-09-7-0-0007a.vhdl
sed 's/^X//' >s-09-7-0-0007a.vhdl <<'*-*-END-of-s-09-7-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-09-2-6-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the generate label is optional.
X-- JB (DB 9/5/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT_1 is
X port (X,Y: in BIT; Z: linkage INTEGER; COUT: out BIT) ;
Xend ENT_1;
X
Xarchitecture AB_1 of ENT_1 is
X-- L_X_1: block
X component COMP_1
X port(A: in BIT; B: linkage INTEGER; SOUT: out BIT);
X end component ;
X signal S1: BIT ;
X signal S2: INTEGER ;
X begin
X for GP1 in 1 to 5 generate
X C1: COMP_1 port map (X, S2, COUT);
X end generate;
X
X for GP2 in BIT range '0' to '1' generate
X C2: COMP_1 port map (S1, Z, S1);
X end generate;
X
X-- end block ;
Xend AB_1;
X
X
*-*-END-of-s-09-7-0-0007a.vhdl-*-*
exit
--
Steve Grout @ MCC VLSI CAD Program, Austin TX. [512] 343-0860
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout