marc@CS.UCLA.EDU (09/26/87)
There has been a great deal of discussion lately on Error Correcting Codes. I haven't seen anything on implementation issues though. We are presently involved with a couple of designs which make use of Hamming code. More specifically, I am working on the design of a 32-bit processor with fault-tolerance capabilities (CMOS). We use a chain of transmission gates in order to obtain the parity bits necessary to encode the Hamming bits. The timing is not great but the design is quite simple. Does anyone have a fast method for encoding Hamming bits? Something in the order of 30ns-40ns for 3 micron technology seems like a good target for us. Marc Tremblay marc@CS.UCLA.EDU ...!(ihnp4,ucbvax)!ucla-cs!marc Computer Science Department, UCLA
mark@mips.UUCP (09/27/87)
In article <8348@shemp.UCLA.EDU>, marc@CS.UCLA.EDU (Marc Tremblay) writes > ... More specifically, I am working on the design of a > 32-bit processor with fault-tolerance capabilities (CMOS). > We use a chain of transmission gates in order to obtain > the parity bits necessary to encode the Hamming bits. > The timing is not great but the design is quite simple. > Does anyone have a fast method for encoding Hamming bits? > Something in the order of 30ns-40ns for 3 micron technology > seems like a good target for us. There's a good paper on a 1 Megabit ROM which does error correction on 64-bit words. The worst-case check bit required computing parity over 33 bits; they did this using a tree (but not a binary tree). Theirs had 2 levels; the first level was 4 "8 input XOR gates" and the second level was 5 "5 input XOR gates" (33rd bit brought in at 2nd level). {An "N-input XOR gate" computes odd parity over N bits}. Their N-input XOR gates were implemented as dual rail (parity and parity-bar are computed) pass transistor networks, with a sense-amp on the output for speed. See Figure 3 of the paper below. As I recall from the oral presentation (this tidbit isn't in the text of the paper), delay thru the ECC circuitry is about 10 nsec. The access time of the entire ROM is 70 nsec so this figure sounds about right. They used 1.5 micron CMOS. ===> Harold Davis, "A Word-Wide 1Mb ROM with Error Correction", ===> IEEE International Solid-State Circuits Conference ("ISSCC"), ===> Digest of Technical Papers, Feb. 1985, pp. 40-41. -- -Mark Johnson *** DISCLAIMER: The opinions above are personal. *** UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark TEL: 408-720-1700 x208 US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086