keithl@loop.uucp (Keith Lofstrom;;;628-3645) (10/02/90)
Any good or bad ASIC/Custom IC vendor stories out there? How about mask, package, or test shops? Prices? Yield? Reliability? Honesty? Vendors seem unnecessarily reticent about quoting prices publically; can anyone think of a good way to collect this data without angering them? -- Keith Lofstrom keithl@loop.uucp ...!sun!nosun!loop!keithl (503)628-3645 KLIC --- Keith Lofstrom Integrated Circuits --- "Your Ideas in Silicon" Design Contracting in Bipolar and CMOS - Analog, Digital, and Power ICs
grege@gold.GVG.TEK.COM (Greg Ebert) (10/04/90)
keithl@loop.uucp (Keith Lofstrom;;;628-3645) writes: > >Vendors seem unnecessarily reticent about quoting prices publically; can >anyone think of a good way to collect this data without angering them? > > I sympathize. I went through this silliness about 2 years ago. I just asked them for quotes on several die sizes in the same package. You can get a couple of data points and then assume price is directly proportional to yield. Then, I plotted yield vs. size assuming Poisson distribution, and again using Seed's algorithm. By the way, when I say yield, I mean the total number of good die per wafer, not just the percentage of good die. Thus, you need to estimate the number of die/wafer. For a given technology, cost/wafer is basically fixed. But, you can pit 2 vendors against eachother. Vendor 'L' would quote one price, then vendor 'V' would quote a lower one, both vendors knowing that they were competing against eachother. I told vendor 'L' that vendor 'V' was cheaper. Vendor 'L' would ask, "Well, what did they bid ?". I'd say, "Well, I can't tell you the exact price, but it's between $18.43 and $18.45 per chip". This would go on for a few iterations. . . . For gate arrays and standard cells, you will find lower prices from Japanese companies, but you will find that their macrocell libraries aren't as highly developed as U.S. vendors. All vendors have the same basic cell libraries (flip-flops, gates, muxes, and decoders), but differ wildly on things like multipliers, CPU's, UARTS, etc. Many vendors will provide design 'kits' which let you use Daisy, ViewLogic, or other schematic capture packages for design entry. Be careful. I have ALWAYS seen problems during database conversion. Another hassle is back- annotation of layout delays, etc. It's probably cheaper to use a 'design kit' but it's more hassle than using the vendor's CAD tools. An alternative is to do work inside the vendor's design center. I strongly recommend this approach if (a) It's the first design with the vendor, and (b) you are considering purchasing their tools. Some vendors will loan their tools free of charge for a 'test drive', especially if you book a design with them. I'm a bit reluctant to name vendors because there are so many out there which I haven't used, but have outstanding reputations. Here are the ones I have worked with: LSI Logic - Very picky with design signoff, but once this step is reached, you will have a chip with no surprises. Definitely a WYSIWYG (what-you- simulate-is-what-you-get) vendor. Good toolset. Somewhat higher in price. VLSI Technology - More flexible than LSI Logic, slightly better toolset, and slightly lower price. National Semiconductor - Used as a 'fab for hire', ie "here's my PG tape, now give me my wafers". Aggressive pricing. ------------------------------------------------------------------------- ##### {uunet!tektronix!gold!grege} Register to vote, then ## | ## grege@gold.gvg.tek.com vote responsibly # | # # /|\ # Support the First Amendment, not the party that attacks it #/ | \# "I was, BANNED in the USA" - 2 Live Crew #######
speyer@joy.cad.mcc.com (Bruce Speyer) (10/04/90)
In article <1537@gold.GVG.TEK.COM> grege@gold.GVG.TEK.COM (Greg Ebert) writes: >National Semiconductor - Used as a 'fab for hire', ie "here's my PG tape, now >give me my wafers". Aggressive pricing. This is not accurate. They offer a range of services like the other vendors too. It is not unusual for them to do at least the physical layout and test. Bruce Speyer / MCC CAD Program WORK: [512] 338-3668 3500 W. Balcones Center Dr., Austin, TX. 78759 ARPA: speyer@mcc.com
elliott@optilink.UUCP (Paul Elliott x225) (10/09/90)
In article <1537@gold.GVG.TEK.COM>, grege@gold.GVG.TEK.COM (Greg Ebert) writes: > Many vendors will provide design 'kits' which let you use Daisy, ViewLogic, > or other schematic capture packages for design entry. Be careful. I have > ALWAYS seen problems during database conversion. Another hassle is back- > annotation of layout delays, etc. It's probably cheaper to use a 'design kit' > but it's more hassle than using the vendor's CAD tools. An alternative is to > do work inside the vendor's design center. I strongly recommend this approach > if (a) It's the first design with the vendor, and (b) you are considering > purchasing their tools. Some vendors will loan their tools free of charge for > a 'test drive', especially if you book a design with them. I've recently done some gate array design using Motorola's 2 micron cmos family, on a Daisy "personal logician" station. We used the Motorola design kit (Motorola-provided libraries and post-processing tools) for the Daisy environment. We had no problems with database conversion, or with delay back-annotation. In fact, the process went extremely smoothly. The chips even WORKED! The only problems were: 1) Daisy software bugs. 2) The Motorola design kit was for earlier versions of the Daisy tools than the latest (but we had the working versions on hand). Daisy support problems, and the desire for broader ASIC vendor options led us to get Mentor systems for our next designs. I'm doing another Motorola chip (1 micron cmos), and will report on the process (if anyone is interested). -- Paul M. Elliott Optilink Corporation (707) 795-9444 {uunet, pyramid, tekbspa}!optilink!elliott "an archetypal entity..., superimposed on our culture by a cosmic template."