djr@cs.ed.ac.uk (David Rees) (05/06/91)
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August 19-22, 1991
Edinburgh, Scotland
Come to Edinburgh this summer for VLSI 91! Participate in the latest
in the VLSI series of conferences and also enjoy side activities such
as the Edinburgh Festival, Fringe, Tattoo, Golf, Whiskey tasting etc.
Keynote Speakers:
Iann Barron, Bristol : "The Last 10 years - the Next 10 Years?"
Richard Newton, UC Berkeley : "Has CAD for VLSI Reached a Dead End?"
Mitsumasa Koyanagi, Hiroshima Univ. : "A New Chip Architecture for
VLSI - Optical Coupled 3D Common Memory & Optical Interconnections"
Submitted Papers (20-22nd August):
Session 1 - Arithmetic
"A Regularly Structured 54-bit Modified Wallace Tree Multiplier",
T.Sato, N.Nakajima, T.Sukemura & G.Goto, Fujitsu
"OCAPI: A Circuit for On-line radix 2 High Precision Arithmetic",
A.Guyot & Y.Kusumaputri, INPG Grenoble
Session 2 - Digital Signal Processing
"The Design of a highly pipelined 2nd order IIR Filter Chip",
O.McNally,J.McCanny & R.Woods,Queen's Univ. Belfast
"Design of a Fully Parallel Viterbi Decoder",
J.Sparso, S.Pedersen & E.Paaske, TU Denmark
"Pipelined Bit-Serial Synthesis of Digital Filtering Algorithms",
R.Nagalla & L.E.Turner, Univ. of Calgary
Session 3A - Formal Methods
"Symbolic Model Checking with Partitioned Transition Relations",
J.R.Burch, E.M.Clarke & D.E.Long, CMU
"Integration of Formal Methods with System Design",
E.M.Mayger & M.P.Fourman, Abstract Hardware Ltd.
"Deriving Bit-Serial Circuits in Ruby",
G.Jones & M.Sheeran, Univ. of Oxford
"Automating Most Parts of Hardware Proofs in HOL",
K.Scheider, R.Kumar & T.Kropf, Univ. of Karlsruhe
Session 3B - Physical Design
"DOMINO: Deterministic Placement Improvement with Hill-Climbing
Capabilities", K.Doll, F.M.Johannes & G.Sigl, TU Munich
"A Flow-Oriented Approach to the Placement of Boolean Networks",
S.Mayrhofer, M.Pedram & U.Lauther, Siemens AG
"Bounds on Net Delays for Physical Design of Fast Circuits",
H.Youssef et al., King Fahd & Minnesota Univs.
"Area Minimisation of IC Power/Ground Nets by Topology Optimis-
ation", K-H.Erhard & F.M.Johannes, Siemens AG & TU Munich
Session 4A - Simulation
"On Distributed Logic Simulation using Time Warp",
H.Bauer et al., TU Munich & Bell-Northern
"An Integrated Environment for the Design and Simulation of Self-"
Timed Systems, E.L.Brunvand & M.Starkey, Univ. of Utah
"A General Purpose Network Solving System",
T.J.Kazmierski et al., Univ. of Southampton
Session 4B - Vision and Neural Architectures
"VLSI Vision Systems",
P.B.Denyer, D.Renshaw et al., Univ. of Edinburgh
"A Distributed Neural Network Silicon Compiler",
J.Trilhe, G. Saucier et al., SGS Thomson
"A VLSI Module for Analog Adaptive Neural Architectures",
D.D.Caviglia, M.Valle & G.M.Bisio, Univ. of Genoa
Session 5 - High-Level Synthesis
"Partitioning-Based Allocation of Dedicated Datapaths in Archi-
tectural Synthesis for High Throughput", W.Geurts, IMEC
"A New Approach to Multiplexer Minimisation in the CALLAS Synth-
esis Environment", N.Wehn, J.Biesenack & M.Pilsl, Siemens AG
Session 6A - Modelling for Synthesis
"Meta VHDL for Higher Level Controllers Modelling and Synthesis",
A.Jerraya, P.G.Paulin & S.Curry, BNR Ottawa
"Towards a Formal Model of VLSI Systems Compatible with VHDL",
P.A.Wilsey et al., Univ. of Cincinnati
"Hardware Design using CASE Tools",
W.Glunz & G.Venzl, Siemens AG
Session 6B - Processor Design
"A VLSI Design System for the Control of High Performance Combus-
tion Engines", A.Laudenbach, M.Glesner & N.Wehn, TU Darmstadt
"A Fully Integrated Systolic Co-Processor",
P.Frison & D.Lavenier, IRISA
"Parallel Architecture and VLSI Implementation of a 80Mhz 2D-DCT/
IDCT Processor", W.Liebsch & K.Boettcher, Heinrich Hertz Inst.
Session 7 - RT-level Synthesis
"Exact Redundant State Registers Removal Based on Binary Decision
Diagrams", B.Lin & A.R.Newton, UC Berkeley
"Resource Restricted Global Scheduling",
P.F.Yeung & D.J.Rees, Univ. of Edinburgh
"Synthesis of Intermediate Memories needed for the Data Supply to
Processor Arrays", M.Schoenfeld et al., Univ. of Hannover
"Workspace and Methodology Management in the Octools Environment",
M.Zanella & P.Gubian, Univ. di Brescia
Session 8A - Routing
"Single-Level Wiring for CMOS Functional Cells",
J.Madsen, TU Denmark
"An Over-the-Cell Channel Router",
R.R.Pai & S.S.S.P.Rao, Indian Inst. of Technology
"Switchbox Routing by Pattern Matching",
M.Starkey & T.M.Carter, Univ. of Utah
Session 8B - VLSI Arrays
"GPFP: A SIMD PE for Higher VLSI Densities",
D.Beal & C.Lambrinoudakis, Univ. of London
"Input/Output Design for VLSI Array Architectures",
W.P.Burleson & L.L.Scharf, Univ. of Colorado
"Comparing Transformation Schemes for VLSI Array Processor Design",
A.F.Nielsen et al., Aalborg Univ.
Session 9 - Circuit Design 1
"Pass-Transistor Self-Clocked Asynchronous Sequential Circuits",
F.Aghdasi, Univ. of Bristol
"Theoretical and Practical Issues in CMOS Wave Pipelining",
C.T.Gray et al., North Carolina State Univ.
Session 10 - Circuit Design 2
"Automatic Interfacing of Synchronous Modules to an Asynchronous
Environment", N.Awad & D.Smith, SUNY
"How to Compare Analog Results",
B.Klaassen, GMD
"Application of Scan-Based DFT Methodology for Detecting Static
and Timing Failures in VLSI, B.I.Dervisoglu, Apollo Computer Inc.
Session 11 - Logic Synthesis and Timing Optimisation
"Identification and Resynthesis of Pipelines in Sequential Net-
works", S.Dey, F.Brglez & G.Kedem, Duke Univ. & MCNC
"Hierarchical Retiming Including Pipelining",
A.van der Werf et al., Philips NV
"Preserving Don't Care Conditions During Retiming",
E.M.Sentovich & R.K.Brayton, UC Berkeley
Session 12 - Fault Tolerant Arrays
"A Fault Tolerant and High Speed Instruction Systolic Array",
M.Schimmler & H.Schmeck, Christian-Albrechts Univ.
"A Reconfigurable Fault Tolerant Module Approach for Reliability
Enhancement for Processor Arrays", L.Guoning, Univ. of Oslo
"The WASP 2 Wafer Scale Integration Demonstrator",
I.P.Jalowiecki & S.J.Hedge, Brunel Univ.
Programme Chairman:
Prof. Arne Halaas, University of Trondheim
Programme Committee:
G.Birtwistle (Canada), P.B.Denyer (UK), M.Fourman (UK), C.E.Goutis
(Greece), J.P.Gray (UK), P.Michel (Germany), S.Murai (Japan),
T.Nishimukai (Japan), G.Saucier (France), C.H.Sequin (USA),
J.Staunstrup (Denmark), T.Yanagawa (Japan)
Tutorials (August 19) :
Richard Newton, UC Berkeley : "High level synthesis:
Mike Gordon, Cambridge Univ. : "Mechanized Reasoning and Hardware Design"
Alain Martin, Caltech : "Compiling Silicon from Processing Descriptions"
Robert Kupin, CLSI : "VHDL"
Chip Art Exhibition:
Integrated circuits can be seen as wonders of modern technology. They
can also be looked upon as works of art in miniature. Designers are
invited to submit integrated circuits for a chip art contest. Designs
will be displayed to the public during the Edinburgh International
Festival and prizes will awarded to those adjudged the best. A wall-
mounted montage of an enlarged layout of the chip, the silicon itself
and a description of the function of the chip in less than 100 words
must be available for display by 31st July 1991.
Edinburgh International Festival (11th - 31st August 1991):
Now in its 45th year, the Edinburgh Festival is renowned as the largest
festival of the arts in the world. The ``Official'' Festival which
includes an international programme of Opera, Orchestral Music, Theatre,
Dance and Fine Art performed by leading artists from all over the world
is complemented by the famous Fringe Festival. Over 1000 shows from
student comedians to the latest experimental drama. Also associated with
these events is the world's oldest Film Festival, a Jazz Festival and a
Television Festival.
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Tutorials: am : High Level Synthesis ____ or Mechanised Reasoning ____
pm : Asynchronous Synthesis ____ or VHDL ____
(one session 100 pounds; two sessions 150 pounds)
Conference : before 17 May after 17 May
delegate : 225 pounds ____ 275 pounds ____
student : 75 pounds ____ 75 pounds ____
Accommodation :
Mount Royal Hotel, Princes St.(3 star),
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tel. +44 31 557 2478
fax. +44 31 557 5749
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----------------------------------------------------------------------------mpe@shamash.cdc.com (Mike Ebsen) (05/07/91)
With all of the cross-posting these two groups have in common I must ask a rather simple question... should comp.lsi.xxxxxxx groups be combined to reduce bandwidth and help focus attentions to a single source of data flow. There is just too much cross-posting and not enough new (unique) threads to justify maintaining two or more news groups. Just one man's opinion mpe@shamash.cdc.com