sundar@mipos2.intel.com (Sundar Iyengar~) (06/08/89)
Has anybody tried applying mixed mode simulation techniques to chip design? In a mixed mode model, different parts of the model would be at different abstraction level. Board designers certainly use such techniques. I am not a board designer, but let me describe what I think the usual design practice is. For a board design, typically one or more chips are still not available, and hence bus functional models of the missing chips are used in the simulation. At this stage, only the bus logic is designed and debugged. However, to examine performance trade-offs, the real chips or full functional models are requir ed so that the actual activity on the system bus could be monitored. Full functional models are either too time consuming to work with or they are not available. Hence, the designers usually end up waiting for the real chips. As one can see, there is a clear separation between debug and performance tweak activities. It seems to me that, in order to use mixed mode simulation techniques at the chip level, the same separation has to be achieved. However, the chip designers usually do not separate debug from performance tweaks. In order to fully test a module, clock by clock description of all activities at the module interface is necessary. However, if the design outside the module under test is at a more abstract level, a full description of the interface activity may not be possible. Given this, is mixed mode simulation viable for chip design? Any comments? Sundar Iyengar Microprocessor Design UUCP: intelca!mipos3!mipos2!sundar Intel, SC4-59 ARPA: sundar@mipos2.intel.com 2625, Walsh Avenue CSNET: sundar@mipos2.intel.com Santa Clara, CA 95051 AT&T: O: (408) 765-5206 Disclaimer: The questions have been raised for reasons of cultural enrichment only.
vicc@unix.cie.rpi.edu (VICC Project (Rose)) (06/09/89)
In article <228@mipos3.intel.com>, sundar@mipos2.intel.com (Sundar Iyengar~) writes: > > Has anybody tried applying mixed mode simulation techniques to chip design? > > Any comments? > > Sundar Iyengar Microprocessor Design > Yes I have done some mixed mode simulation for chip design. I have used LASAR in these simulations. Mixed mode simulation seems to be most usefull in simulating complex or time consuming structures which are not on the critical path. If you are not designing a chip which must push the limits of the technology (ie tweaking is not needed) then mixed mode simulation also has some use. Frank Filz Rensselaer Polytechnic Institute Center for Integrated Electronics
sdg@uts.amdahl.com (Subrata Dasgupta) (06/10/89)
>Given this, is mixed mode simulation viable for chip design? > >Any comments? > Mixed mode simulation is definitely viable and has been tried in chip design at various organizations. I don't see any reason why it would be possible to apply mixed mode simulation to a board-level design and not be feasible for chip design. Speaking from my own experience at Duke University, we simulate VLSI chips using Leonardo (a mixed-mode simulator). It is possible to do functional/behavioral, gate-level, and circuit-level simulation using Leonardo. A typical VLSI design cycle consists of simulation, design, and testing iterated several times before a design becomes fabricated. It is in this process that mixed-level simulation can be very useful. The typical stages in the design process supported by Leonardo are: chip prototyping: -this includes functional modeling and register-level design evaluation; standard cell layout: -gate level simulation of the entire design, followed by circuit level simulation. At every stage, the designer has the option of replacing a section of the chip by it's corresponding high-level model. So, to answer the original question, yes, mixed-level design is not only feasible for chip design it is more so than board-level design because of the reduced requirements on memory resources over board-level design. Subrata (sdg@uts.amdahl.com)
marco@buengc.BU.EDU (Marco Zelada) (06/10/89)
In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes: > >Mixed mode simulation is definitely viable and has been tried in chip >design at various organizations. I don't see any reason why it would >be possible to apply mixed mode simulation to a board-level design and >not be feasible for chip design. Speaking from my own experience at >Duke University, we simulate VLSI chips using Leonardo (a mixed-mode >simulator). It is possible to do functional/behavioral, gate-level, >and circuit-level simulation using Leonardo. Where could one get the Leonardo simulator you mention here ? I would be very interested in trying it out on a project I am working on right now. Thank you in advance. -- ___________________________________________________________________________ | Name: Marco Zelada | Tel: 617 353 9882, Fax: 353 6322 | | Group: VLSI CAD Research Laboratory | E-mail: marco@buengc.bu.edu | | Dept: Electrical & Computer Eng. | US-Mail: 44 Cummington St. | | Org: Boston University | Boston MA, 02215 | ---------------------------------------------------------------------------
sdg@uts.amdahl.com (Subrata Dasgupta) (06/11/89)
In article <3102@buengc.BU.EDU> marco@buengc.bu.edu (Marco Zelada) writes: >In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes: >> >>Mixed mode simulation is definitely viable and has been tried in chip >>design at various organizations. I don't see any reason why it would >>be possible to apply mixed mode simulation to a board-level design and >>not be feasible for chip design. Speaking from my own experience at >>Duke University, we simulate VLSI chips using Leonardo (a mixed-mode >>simulator). It is possible to do functional/behavioral, gate-level, >>and circuit-level simulation using Leonardo. > > Where could one get the Leonardo simulator you mention here ? >I would be very interested in trying it out on a project I am working >on right now. The Leonardo simulator I used was being developed and wasn't released as a tool to organizations outside Duke. This was about 10 months back. One of the original goals of the project was to incorporate it as part of the OASIS (Open Architecture Silicon Implementation System) tools developed jointly at MCNC and Duke. I'm not sure if at this time it is available or not. But if it is, you can get more informayion by sending email to: Franz Brglz (MCNC) brglz@mcnc.org or Gershon Kedem at kedem@cs.duke.edu. You can also get more info. about the status of the Leonardo system from Jack Briner (jvb@cs.duke.edu) who was the principle person behind the project. Subrata Dasgupta
jvb@romeo.cs.duke.edu (Jack V. Briner) (06/12/89)
In article <3102@buengc.BU.EDU> marco@buengc.bu.edu (Marco Zelada) writes: >In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes: >> >>Mixed mode simulation is definitely viable and has been tried in chip >>design at various organizations. I don't see any reason why it would >>be possible to apply mixed mode simulation to a board-level design and >>not be feasible for chip design. Speaking from my own experience at >>Duke University, we simulate VLSI chips using Leonardo (a mixed-mode >>simulator). It is possible to do functional/behavioral, gate-level, >>and circuit-level simulation using Leonardo. > > Where could one get the Leonardo simulator you mention here ? >I would be very interested in trying it out on a project I am working >on right now. > > Thank you in advance. > >-- Leonardo is part of the OASIS package to be released by MCNC (Microlelectronics Center of North Carolina) at the end of the summer. The package includes a mixed level simulator, a fault simulator, standard cell placement and route, and a design description language. The mixed level simulator (which I developed) is an off shoot of Chris Terman's (MIT) RSIM. Improved transistor switch level modeling is provided by Mark Horowitz and C.Y. Chu (Stanford). The high level modelling language is an enhanced C. Simulation control may be done through C modules or from an simple interpreter. Mixed level extraction from Magic, as well as gate level compiled simulation tools, are included. I will provide more details when we are ready for release. A parallel version of the simulator running on BBN's Butterfly is in the offing and will be available early next year (after I have finished my Ph.D.).
jimmc@sci.UUCP (Jim McBeath) (06/14/89)
References: <228@mipos3.intel.com> Silicon Compiler Systems has been selling a mixed mode simulator specifically designed for IC development for a number of years. It provides simulation capabilities from abstract functional models down to spice level. We have a lot of customers, so it is clearly a viable thing to do. Jim McBeath {decwrl|oliveb|weitek|auspyr}!sci!jimmc Silicon Compilers Systems Corporation (408)371-2900 2045 Hamilton Avenue, San Jose CA 95125