[comp.lsi] notes on 64Mbit DRAM paper from Hitachi

mark@mips.COM (Mark G. Johnson) (06/13/90)

I attended the VLSI Circuit Symposium last Wednesday in Honolulu,
where Hitachi workers presented one of their papers on the
"1.5V Circuit Technology for 64Mb DRAM."

Some notes on the presentation:

    1.  The authors are careful to say they describe a *design* for
        a DRAM.  Not a physically-realized chip.

    2.  Data presented was again carefully stated to be from either
        circuit simulation, or measurements on a 32Kbit test array.
        A full 64Mbit DRAM chip hasn't been built or tested.

    3.  External supply voltage can be 3.3V, regulated on-chip
        down to 1.5V.  Or it can be 1.5V directly.  It can't be 5.0V.

    4.  The design is CMOS.  (Not BiCMOS.)

    5.  Lithography is E-beam direct write on wafer.  Which is a good
        thing because the diesize is 9.74mm by 20.28mm -- afficianados
        will recognize this as being much larger than any available
        optical-lithography wafer stepper's fieldsize.

    6.  If you convert 9.74mm into English units you'll find the die
        is 383 mils wide.  Making it difficult to fit into a DIP or
        ZIP that is backward compatible to 16k, 64k, 256k, etc.

    7.  The design uses 0.3 micron features, but transistor channel
        lengths are 0.5um (N) and 0.6um (P).  Gate oxide is 65 angstroms.

    8.  They were proud of three circuit designs, which formed the bulk
        of the presentation: {1} a half-VDD bias circuit with very low
        output impedance and small power consumption; {2} a bootstrapped
        wordline, high-voltage driver with high boost ratio; {3} a
        secondary sense-amp operated in a current mode, to prevent
        the dT = dV * C/I problem of voltage mode signalling on the very
        long matrix I/O wires.  Primary sense amp is still the traditional
        charge-mode F/F.

    9.  Old timers in the audience recognized Hitachi's circuit idea
        number {2} as having been previously used (in identical circuit
        topology to the Hitachi figure 4) back in 1978 on 16k NMOS DRAM
        designs at Intel, Mostek, and Motorola.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}