speck@VLSI.CALTECH.EDU (Don Speck) (12/07/86)
I'm designing a dRAM in Mosis SCMOS, and I'm finding that the sticky part is generating a properly controlled current for the sense amp. With some dependent sources (in spice2G.6), I can determine what current I need, and what gate voltage waveform will produce such a current; but I can't figure out how to synthesize that voltage waveform. The current starts at the saturation current of a minimum transistor, builds slowly, (taking 60 transit times to double) but with the rate of increase going up all the time, reaching 50 times the original current after 120 transit times. The voltage waveform to produce this looks like: | _ | | - | _ | _ | _- | __- | ___-- | ______----- |_______________---------- Vth-| | |____________________________________________________ It looks a lot like an exponential decay to the enhancement threshold, but time-reversed. I've tweaked together circuits (in spice) that produce the right current waveform, but the waveshape breaks down miserably if the supply voltage changes. Commercial dRAM's work over fairly wide voltage ranges, surely this problem has been solved before... Any suggestions? How do real dRAM designers make their sense ramp generators? Don Speck speck@vlsi.caltech.edu {seismo,rutgers,ames}!cit-vax!speck