grout@cadillac.stars.flab.Fujitsu.JUNET (Steve Grout) (07/13/88)
This is Chapter 05 of a 1076-1987 VHDL test suite which was translated
from an 7.2 VHDL version test suite
developed by Intermetrics under funding by the DoD. These tests
have been verified todate mainly against a VHDL 'recognizer' so they
may yet have problems with VHDL semantics. They consist of two
classes of tests,
ERROR Tests: - those which start with 'e' should result in VHDL errors
at the spot in them where there is a comment about error being expected.
SIMPLE Tests: - those which start with 's' should analyze or compile cleanly.
These tests are being shared back to industry in hopes of getting together
a joint set of tests, checked out and verified, which we can all use to
make sure our various VHDL CAD tools work correctly.
Your comments and especially constructive criticism is urgently requested
via any way we can get it. All replies and resulting changes/updates will
be posted back to the same places these tests were originally posted.
Thanks for your support!
--Steve Grout, MCC CAD Program. (512)338-3516, grout@mcc.com
---- Cut Here and unpack ----
#!/bin/sh
#
# This is a 'shar' archive. Cut out everything above the line
# and unpack them with /bin/sh, i.e., using a command like:
# % sh < {the contents of this message after cutting}
#
#
echo "--------------------------------------------------"
echo "Starting to extract Chapter 05 of a 1076-1987 VHDL"
echo " translated DoD/Intermetrics test suite...."
echo "--------------------------------------------------"
echo x - TEST-SYNOPSIS.text
sed 's/^X//' >TEST-SYNOPSIS.text <<'*-*-END-of-TEST-SYNOPSIS.text-*-*'
X------------------------------------------------------------------------
XChapter: Chapter 05 - Specifications
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
X Paragraph: Specifications - 6.1 -->
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
X Paragraph: Attribute specifications - 6.1.1 --> 5.1
X------------------------------------------------------------------------
XTest: e-05-1-0-0001a.vhdl
X-- Check that the expression in an attribute specification must be a generic
X-- expression.
XTest: e-05-1-0-0002a.vhdl
X-- Check that the base type of the generic expression in an attribute
X-- specification must be the same as or implicitly convertible to the
X-- type mark of the attribute declaration.
XTest: e-05-1-0-0003a.vhdl
X-- Check that the attribute designator in an attributre specification must be a
X-- simple name which has been previously declared in an attribute declaration.
X-- As a special case, check that no attribute specification is permitted for
X-- the predefined attribute RANGE nor for any of the following which have not
X-- been redefined in an attribute declaration: LOW, HIGH, LEFT, RIGHT, POS, VAL,
X-- SUCC, PRED, LENGTH, BASE, DELAYED, STABLE, QUIET, LAST_VALUE,
X-- CHILDLESS, STRUCTURE.
XTest: e-05-1-0-0004a.vhdl
X-- Check that entity class specified in the entity specification must match
X-- an entity class in the entity class list in the corresponding attribute
X-- declaration.
XTest: e-05-1-0-0005a.vhdl
X-- Check that the entity name list in an attribute specification for an
X-- attribute of an entity may be a design unit must contain only the
X-- name of the immediatly encloseing such entity. That is, check
X-- that an attribute specification inside one such entity must not
X-- specify another such entity.
XTest: e-05-1-0-0006a.vhdl
X-- Check that the entity name list in an attribute specification for entity
X-- class type, object, or label may only contain the names of entities whose
X-- declarations precede the attribute specification immediately within the
X-- same declarative part.
XTest: e-05-1-0-0007a.vhdl
X-- Check that only the names of entities which belong to the specified entity
X-- class are permitted in an entity name list of an attribute specification.
XTest: e-05-1-0-0008a.vhdl
X-- Check that if an attribute specification has an entity name list the
X-- attribute is only inherited by entities which are included in the
X-- entity name list
XTest: e-05-1-0-0009a.vhdl
X-- Check that if an attribute specification for an attribute of an entity which
X-- may be a design unit has no entity name list the attribute is inherited
X-- only by the immediately enclosing such entity.
XTest: e-05-1-0-0010a.vhdl
X-- Check that if an attribute specification for entity class type, object, or
X-- label has no entity name list the attribute is inherited only by entities
X-- which are of the specified entity class and whose declarations precede the
X-- attribute specification immediately within the same declarative part.
XTest: e-05-1-0-0011a.vhdl
X-- Check that no more than one attribute specification is allowed for any one
X-- attribute of any one entity. As a special case check that an attribute
X-- specification which specifies an alias counts as the one permitted attribute
X-- for the corresponding entity. As a special case check that an attribute
X-- specification with no entity name list must not follow within the same
X-- declarative part any attribute specification, with or without a name list,
X-- for the same entity class.
XTest: e-05-1-0-0012a.vhdl
X-- Check that an attribute specification for a design entity can appear only
X-- immediatly within the declarative region of an interface declaration.
XTest: e-05-1-0-0013a.vhdl
X-- Check that an attribute specification for a body can appear only immediatly
X-- within the declarative part of a body declaration. As a special case
X-- check for attribute specifications for attributes of entity class body in
X-- the declarative part of the body's outermost block statement and of the
X-- associated interface declaration.
X-- NOTE : That is, check that there is currently no legal placement for
X-- attribute of bodies.
XTest: e-05-1-0-0014a.vhdl
X-- Check that an attribute specification for a package can appear only
X-- immediately within the declarative part of a package declaration.
XTest: e-05-1-0-0015a.vhdl
X-- Check that an attribute specification for a subprogram can appear only
X-- immediately within the declarative region of a subprogram declaration
X-- even when the subprogram is declared inside a package.
XTest: e-05-1-0-0016a.vhdl
X-- Check that an attribute specification for a type, port, signal, variable,
X-- constant or labeled entity can appear only immediately within a declarative
X-- part where a preceding declaration of an entity of the specified entity class
X-- appears. As a special case check that such an attribute specification is not
X-- permitted in a declarative part when there is no such preceding entity
X-- declaration.
XTest: e-05-1-0-0016b.vhdl
X-- Check that an attribute specification for a type, port, signal, variable,
X-- constant or labeled entity can appear only immediately within a declarative
X-- part where a preceding declaration of an entity of the specified entity class
X-- appears. As a special case check that such an attribute specification is not
X-- permitted in a declarative part when there is no such preceding entity
X-- declaration.
XTest: e-05-1-0-0017a.vhdl
X-- Check that references to undefined attributes are not permitted.
X-- That is, check that both the attribute declaration and an attribute
X-- specification must precede all references to that attribute.
XTest: s-05-1-0-0001a.vhdl
X-- Check that the entity name list in an entity specification is optional.
XTest: s-05-1-0-0002a.vhdl
X-- Check that attribute specification are permitted for all user-defined
X-- attributes.
XTest: s-05-1-0-0003a.vhdl
X-- Original file name: S-05-1-1-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that attribute specification for attributes of entities which may
X-- be design units may appear in any number of declarations for design units
X-- of the specified entity class as long as each has entity name list.
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
XTest: s-05-1-0-0004a.vhdl
X-- Check that an entity inherits an attribute if the declaration
X-- of the entity preceeds within the same declarative region or encloses
X-- an attribute specification for that attribute which either includes that
X-- entity in its entity name list or has no entity name list but specifies
X-- that entity's entity class.
XTest: s-05-1-0-0005a.vhdl
X-- Check that all names which denote an object associated with an attribute
X-- may be used as a prefix of that attribute in an attribute name.
X-- As a special case, check for aliases declared after the attribute
X-- specification and also for attribute specifications which specify the
X-- alias name.
X
X------------------------------------------------------------------------
X Paragraph: Configuration Specifications - 6.1.2 --> 5.2
X------------------------------------------------------------------------
XTest: e-05-2-0-0001a.vhdl
X-- Check that an application specification in an architecture body must
X-- not be a block statement label.
XTest: e-05-2-0-0002a.vhdl
X-- Check that configuration specification in architecture bodies must contain
X-- a binding indication and that there are no next level configurations.
XTest: e-05-2-0-0003a.vhdl
X-- Check that a binding indication is not permitted in a configuration
X-- specification which define the configuration of a block
XTest: e-05-2-0-0004a.vhdl
X-- Check that labels in an instantion list must exist in the related declaraive
X-- region and must correspond to instantiations of the given component.
XTest: e-05-2-0-0005a.vhdl
X-- Check that in a given design unit, no more than one configuration
X-- specification is permitted to define the same component instance or
X-- block statement.
XTest: e-05-2-0-0007a.vhdl
X-- Check that an application specification with no component simple name must
X-- consist of a block statement label which is implicitly declared in the
X-- declarative region related to the corresponding next level configuration.
XTest: e-05-2-0-0008a.vhdl
X-- Check that a Configuration specification with binding indication in
X-- a configuration body must not configure a component instance which is
X-- also configured in the corresponding architectureal body.
XTest: s-05-2-0-0001a.vhdl
X-- Check that in configuration bodies binding indications are optional
X-- in configuration specification of component instances if there is either a
X-- select directive which applies to the corresponding next level consiguration
X-- or configuration specification for the given component instance in the
X-- corresponding architecture body.
XTest: s-05-2-0-0002a.vhdl
X-- Check that a configuration specification in a configuration body may define
X-- the configuration of a block or instances of components.
XTest: s-05-2-0-0003a.vhdl
X-- Check that a configuration specification in an architecture body may
X-- configure component instances.
XTest: s-05-2-0-0004a.vhdl
X-- Check that a configuration specification in a configuration body may
X-- contain both a binding indication and a next level configuration.
XTest: s-05-2-0-0006a.vhdl
X-- Check that in a configuration body the binding indication may be omitted
X-- from a configuration specification which defines a component instance if
X-- there is neither a select directive which applies to the corresponding
X-- next level configuration nor a configuration specification for the given
X-- component instance in the corresponding architecture body.
X
X------------------------------------------------------------------------
X Paragraph: Binding Indication - 6.1.2.1 --> 5.2.1
X------------------------------------------------------------------------
X s-05-2-1-0001a.vhdl
X
X------------------------------------------------------------------------
X Paragraph: Entity Aspect - 6.1.2.1.1 --> 5.2.1.1
X------------------------------------------------------------------------
XTest: e-05-2-1-1001a.vhdl
X-- Check that the entity indication of an entity aspect must not be empty
X-- i.e. no empty parenthesis.
XTest: e-05-2-1-1002a.vhdl
X-- Check that if the entity aspect is "open" then the port map aspect, the
X-- generic aspect, the actual ports aspect, and the actual generics aspect
X-- are not permitted and the body indication of the body aspect must also be
X-- "open".
X
X------------------------------------------------------------------------
X Paragraph: ( Entity and Body Aspect chapters were merged in 1076.)
X------------------------------------------------------------------------
X
X------------------------------------------------------------------------
X Paragraph: Body/Entity Aspect - 6.1.2.1.4 --> 5.2.1.1
X------------------------------------------------------------------------
X (Some tests were deleted as no longer applicable.)
XTest: e-05-2-1-1003a.vhdl
X-- Check that if the entity aspect implies a particular design entity then the
X-- body aspect must not imply a library name which is not a body of the specified
X-- kind associated with the design entity implied by the entity aspect.
XTest: s-05-2-1-1004a.vhdl
X-- Check that if identification of the design entity is not deferred then the
X-- body aspect may imply any body of the specified kind which is associated
X-- with the implied design entity.
XTest: s-05-2-1-1001a.vhdl
X-- Check that the body indication of a body aspect may be the keyword "OPEN".
X
X (The Map and Actual generics/ports Aspect chapters were combined in 1076.)
X
X------------------------------------------------------------------------
X Paragraph: Port Map and Generic Map Aspects - 6.1.2.1.2 --> 5.2.1.2
X------------------------------------------------------------------------
XTest: e-05-2-1-2002a.vhdl
X-- Check that each interface element from the component declaration must be
X-- as an actual designator and associated with at least one element from
X-- the corresponding design entity.
XTest: e-05-2-1-2003a.vhdl
X-- Check that it is not permitted for any interface element from the
X-- corresponding design entity to be used as a formal designator associated
X-- with more than one interface element from the component declaration.
XTest: e-05-2-1-2004a.vhdl
X-- Check that the mode of each interface element from the component
X-- declaration used as an actual designator must match the mode
X-- of the associated interface element from the corresponding design
X-- entity.
XTest: e-05-2-1-2005a.vhdl
X-- Check that when the binding indication is defaulted the corresponding design
X-- entity must have a port of the same name as each port in the component
X-- declaration and a generic of the same name as each generic in the
X-- component declaration.
XTest: s-05-2-1-2001a.vhdl
X-- Check that in map aspect association lists any actual designator may be
X-- associated with more than one formal designator.
XTest: s-05-2-1-2001b.vhdl
X-- Check that in port map aspect and generic map aspect association lists
X-- postional association elements are not permitted.
X
X------------------------------------------------------------------------
X Paragraph: Actual Ports and Actual Generics Aspects - 6.1.2.1.3 --> 5.2.1.2
X------------------------------------------------------------------------
XTest: s-05-1-2-2001c.vhdl
X-- Check that if an interface element from the interface declaration has a
X-- default value then association by a map aspect or an actual aspect is
X-- optional.
X (Next Level Configuration tests merged with Configuration Declarations.)
X
X------------------------------------------------------------------------
X Paragraph: Next Level Configuration - 6.1.2.2 --> 1.3
X------------------------------------------------------------------------
X (Most of the 7.2 6.2.x Directive tests were deleted as not applicable.)
X e-05-2-2-0001a.vhdl
X
X------------------------------------------------------------------------
X Paragraph: Assert Directives to Concurrent Assert Stmts - 6.2.1 --> 9.4
X------------------------------------------------------------------------
*-*-END-of-TEST-SYNOPSIS.text-*-*
echo x - e-05-1-0-0001a.vhdl
sed 's/^X//' >e-05-1-0-0001a.vhdl <<'*-*-END-of-e-05-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the expression in an attribute specification must be a generic
X-- expression.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage KL is
X-- attribute AT1 of function is INTEGER;
X attribute AT1 : INTEGER;
X function F(i : integer) return integer ;
X function F2 (X:INTEGER) return BIT ;
Xend KL;
X
Xuse KL.all ;
Xpackage body KL is
X function F(i : integer) return integer is
X variable a : integer;
X begin
X return a;
X end F;
Xfunction F2 (X:INTEGER) return BIT is
X-- for AT1 of function use X;
X attribute AT1 of KL : package is X ;
X --ERROR : Specification expression is not a generic expression
Xbegin
X return '0';
Xend F2;
Xend KL;
X
Xpackage KL is
X attribute AT1 : INTEGER;
X function F(i : integer) return integer ;
X function F2 (X:INTEGER) return BIT ;
Xend KL;
X
Xuse KL.all ;
Xpackage body KL is
X function F(i : integer) return integer is
X variable a : integer;
X begin
X return a;
X end F;
X
Xfunction F2 (X:INTEGER) return BIT is
Xbegin
X return '0';
Xend F2;
Xend KL;
X
X
X
Xentity E is
X port (PT :INTEGER;
X PT1 : INTEGER) ;
Xend E;
X
X--with package KL;
Xuse KL.all ;
Xarchitecture BB of E is
X-- ABB : block
X attribute AT2 : INTEGER;
X constant D : boolean := TRUE;
X attribute FOO : INTEGER;
X attribute FOO of D : constant is KL.F(PT1);
X --ERROR : Specification expression is not a generic expression
X begin
X process
X variable B1 : BOOLEAN;
X attribute AT2 of B1 : variable is (PT);
X --ERROR : Specification expression is not a generic expression
X begin
X B1 := B1;
X end process;
X-- end block;
Xend BB;
X
X
*-*-END-of-e-05-1-0-0001a.vhdl-*-*
echo x - e-05-1-0-0002a.vhdl
sed 's/^X//' >e-05-1-0-0002a.vhdl <<'*-*-END-of-e-05-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the base type of the generic expression in an attribute
X-- specification must be the same as or implicitly convertible to the
X-- type mark of the attribute declaration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X port (PT:BOOLEAN) ;
X attribute AT1 : integer;
Xend E;
X
X
Xarchitecture BB of E is
X-- BC : block
X begin
X process
X type TESTSTR is (a,b,c,d) ;
X subtype TESTSTRSUB is TESTSTR range a to c;
X attribute AT2 : TESTSTRSUB;
X constant OK : TESTSTRSUB := A ;
X variable B1 : BOOLEAN ;
X attribute AT1 of E : type is 1.2;
X --ERROR : Specification expression is not the same type as attribute
X -- declaration
X constant REALNUM : REAL := 4.2;
X attribute AT2 of TESTSTR : type is REALNUM;
X --ERROR : Specification expression is not the same type as attribute
X -- declaration
X begin
X B1 := B1;
X end process;
X-- end block BC ;
Xend BB;
X
*-*-END-of-e-05-1-0-0002a.vhdl-*-*
echo x - e-05-1-0-0003a.vhdl
sed 's/^X//' >e-05-1-0-0003a.vhdl <<'*-*-END-of-e-05-1-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the attribute designator in an attributre specification must be a
X-- simple name which has been previously declared in an attribute declaration.
X-- As a special case, check that no attribute specification is permitted for
X-- the predefined attribute RANGE nor for any of the following which have not
X-- been redefined in an attribute declaration: LOW, HIGH, LEFT, RIGHT, POS, VAL,
X-- SUCC, PRED, LENGTH, BASE, DELAYED, STABLE, QUIET, LAST_VALUE,
X-- CHILDLESS, STRUCTURE.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
Xend E1;
X
Xarchitecture ABC of E1 is
X-- BB : block
X attribute A1 : INTEGER;
X signal S1 : BOOLEAN;
X attribute A2 of S1 : signal is 9;
X -- ERROR : no preceding user-defined attribute declaration for A2
X begin
X S1 <= TRUE;
X-- end block BB;
Xend ABC;
X
Xpackage P is
X attribute A3 : BIT;
Xend P;
X
Xentity E2 is
X attribute A3 of E2 : entity is '1';
X -- ERROR : A3 is not visible here
Xend E2;
X
Xentity EE1 is
X generic (i : integer) ;
X type tr is range 1 to 10;
X type enum is (a,b,c);
X type ar is array (1 to I) of Integer;
X subtype senum is enum;
X attribute LOW of tr : type is 1 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute HIGH of tr : type is 10 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute LEFT of tr : type is 1;
X -- ERROR : no preceding user-defined attribute declaration
X attribute RIGHT of tr : type is 10 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute POS of tr : type is 1 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute VAL of tr : type is 1;
X -- ERROR : no preceding user-defined attribute declaration
X attribute SUCC of enum : type is 13 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute PRED of enum : type is 45 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute LENGTH of ar : type is 10 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute BASE of senum : type is enum;
X -- ERROR : no preceding user-defined attribute declaration
Xend EE1;
X
Xentity EE1 is end;
X
Xarchitecture GDUM of EE1 is
X-- HH: block
X signal S1 : Integer;
X attribute DELAYED of S1 : signal is 5 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute STABLE of S1 : signal is 77 ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute QUIET of S1 : signal is FALSE ;
X -- ERROR : no preceding user-defined attribute declaration
X attribute LAST_VALUE of S1 : signal is 1000 ;
X -- ERROR : no preceding user-defined attribute declaration
X begin
X process
X begin
X null;
X end process;
X-- end block;
Xend GDUM;
*-*-END-of-e-05-1-0-0003a.vhdl-*-*
echo x - e-05-1-0-0004a.vhdl
sed 's/^X//' >e-05-1-0-0004a.vhdl <<'*-*-END-of-e-05-1-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that entity class specified in the entity specification must match
X-- an entity class in the entity class list in the corresponding attribute
X-- declaration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F1 ( A : Boolean ) return Boolean ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 ( A : Boolean ) return Boolean is
X attribute AB : Integer ;
X variable Var_bool : boolean;
X
X attribute AB of Var_bool : variable is 5 ;
X -- ERROR : attribute not defined for this entity kind
X
X begin
X return false ;
X end F1;
Xend P ;
*-*-END-of-e-05-1-0-0004a.vhdl-*-*
echo x - e-05-1-0-0005a.vhdl
sed 's/^X//' >e-05-1-0-0005a.vhdl <<'*-*-END-of-e-05-1-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the entity name list in an attribute specification for an
X-- attribute of an entity may be a design unit must contain only the
X-- name of the immediatly encloseing such entity. That is, check
X-- that an attribute specification inside one such entity must not
X-- specify another such entity.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage Att is
X Type T1 is range 1.0 to 5.0;
X Attribute A1 : T1;
X function F1 ( B : in Boolean) return T1 ;
Xend Att;
X
Xuse Att.all ;
Xpackage body Att is
Xfunction F1 ( B : in Boolean) return T1 is
X begin
X return 3.0;
Xend F1;
Xend Att;
X
X-- with package Att;
XUse Att.all;
Xentity E2 is
X port ( PC : in boolean ) ;
X attribute A1 of F1 : function is 5.0 ;
X -- ERROR : only enclosing entities are allowed to be specified in the
X -- entity name list.
Xend E2;
*-*-END-of-e-05-1-0-0005a.vhdl-*-*
echo x - e-05-1-0-0006a.vhdl
sed 's/^X//' >e-05-1-0-0006a.vhdl <<'*-*-END-of-e-05-1-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the entity name list in an attribute specification for entity
X-- class type, object, or label may only contain the names of entities whose
X-- declarations precede the attribute specification immediately within the
X-- same declarative part.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT is
X attribute TOTAL : BOOLEAN;
X attribute NEWER : STRING;
Xend ENT;
X
Xarchitecture ABC of ENT is
X-- BB : Block
X attribute LOCAL : INTEGER;
X attribute LOCAL of T1 : type is 5;
X -- ERROR : declaration of named entity must preceed attribute specification
X -- within the same declarative part
X type T1 is range 1 to 10000;
X attribute TOTAL of P1 : label is TRUE;
X -- ERROR : declaration of label must be implied in declarative part
X -- where the attribute specification appears
X signal S1 : BOOLEAN;
X attribute NEWER of S1 : signal is "FALSE";
X begin
X S1 <= TRUE;
X process
X-- for NEWER of signal S1 use "FALSE";
X attribute NEWER of S1 : signal is "FALSE";
X -- ERROR : declaration of named entity must preceed attribute specificatio
X -- within the same declarative part
X begin
X P1 :
X while TRUE
X loop
X null;
X end loop;
X end process;
X-- end block BB;
Xend ABC ;
X
Xpackage P is
X attribute BAD : REAL;
X type T1 is range 1 downto 0;
Xend P;
X
X-- with package P;
Xuse P.all;
X
X
Xuse P.all ;
Xpackage P is
X function F return REAL ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return REAL is
X attribute BAD of T1 : type is 9.574;
X -- ERROR : declaration of named entity must preceed attribute specification
X -- within the same declarative part
Xbegin
X return 1.0;
X end F;
Xend P ;
*-*-END-of-e-05-1-0-0006a.vhdl-*-*
echo x - e-05-1-0-0007a.vhdl
sed 's/^X//' >e-05-1-0-0007a.vhdl <<'*-*-END-of-e-05-1-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that only the names of entities which belong to the specified entity
X-- class are permitted in an entity name list of an attribute specification.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xuse P.all ;
Xpackage P is
X function F1 return Boolean ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 return Boolean is
X
X attribute ATT : integer;
X type T1 is range 1 to 100000 ;
X
X variable V1 : Integer := 0 ;
X
X attribute Att of T1,V1 : type is 2 ;
X -- ERROR: only name which belong to the entity class are permitted in
X -- an entity name list.
X
X begin
X return false ;
X end F1 ;
Xend P ;
*-*-END-of-e-05-1-0-0007a.vhdl-*-*
echo x - e-05-1-0-0008a.vhdl
sed 's/^X//' >e-05-1-0-0008a.vhdl <<'*-*-END-of-e-05-1-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if an attribute specification has an entity name list the
X-- attribute is only inherited by entities which are included in the
X-- entity name list
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity G is
Xend G;
X
Xarchitecture GB of G is
X-- FF: block
X signal S1, S2 : bit;
X
X type WHFS_Djs is (Mark, Sarah, David, Weasel, Bob, Diane);
X attribute My_DJ : WHFS_DJs;
X attribute My_DJ of S1 : signal is Weasel;
X begin
X process
X variable B1 : boolean;
X begin
X if S2'My_DJ = Weasel then
X -- SEM ERR: Attribute not specified for this object
X B1 := TRUE;
X end if;
X end process;
X-- end block;
Xend GB;
*-*-END-of-e-05-1-0-0008a.vhdl-*-*
echo x - e-05-1-0-0009a.vhdl
sed 's/^X//' >e-05-1-0-0009a.vhdl <<'*-*-END-of-e-05-1-0-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if an attribute specification for an attribute of an entity which
X-- may be a design unit has no entity name list the attribute is inherited
X-- only by the immediately enclosing such entity.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X attribute A1 : Integer ;
X function F1 return Boolean ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F1 return Boolean is
X attribute A1 of F1 : function is 5;
X begin
X return false ;
X end F1;
X
X function F2 return boolean is
X begin
X return False;
X end F2;
Xend P;
X
X-- with package P ;
Xuse P .all;
Xentity SSD is
Xend SSD;
X
Xarchitecture F of SSD is
X-- LL: block
X begin
X process
X variable B1 : boolean;
X begin
X if F2'A1 = 5 then
X -- SEM ERROR: Attribute not specified for this entity name.
X b1 := True;
X end if;
X end process;
X-- end block;
Xend F;
*-*-END-of-e-05-1-0-0009a.vhdl-*-*
echo x - e-05-1-0-0010a.vhdl
sed 's/^X//' >e-05-1-0-0010a.vhdl <<'*-*-END-of-e-05-1-0-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if an attribute specification for entity class type, object, or
X-- label has no entity name list the attribute is inherited only by entities
X-- which are of the specified entity class and whose declarations precede the
X-- attribute specification immediately within the same declarative part.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X type T1 is range 1 to 1000000;
X attribute A1 :INTEGER;
X attribute A1 of all : type is 6;
X type T2 is range 1 to 1000000;
X type T3 is range 0 to T2'A1;
X -- ERROR : attribute not specified for this entity name.
X -- Entity decl must preceed attribute specification.
X
X function F1 return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F1 return BOOLEAN is
X variable V1 : CHARACTER;
X attribute TV1 : T1;
X attribute TV1 of all : variable is 50;
X variable V2 : T1;
X begin
X V2 := V2'TV1;
X -- ERROR : declaration of V2 does not precede attribute specification
X return FALSE;
X end F1;
Xend P;
X
Xuse P.all ;
Xpackage P is
X type T1 is range 1 to 1000000;
X attribute A1 : INTEGER;
X attribute A1 of all : type is 6;
X type T2 is range 1 to 1000000;
X function F1 return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F1 return BOOLEAN is
X variable V1 : CHARACTER;
X attribute TV1 : T1;
X attribute TV1 of all : variable is 50;
X variable V2 : T1;
X begin
X return FALSE;
X end F1;
Xend P;
X
X-- with package P;
Xuse P.all;
Xentity E1 is
X port ( PT : BOOLEAN ) ;
X constant C1 : REAL := 5.0;
X attribute TC1 : REAL;
X attribute TC1 of all : constant is 6.4;
X constant C2 : REAL := 6.2;
Xend E1;
X
Xarchitecture ABB of E1 is
X-- BB : block
X signal S1 : BOOLEAN;
X attribute TS1 : Boolean;
X attribute TS1 of all : signal is FALSE;
X signal S2,S4 : INTEGER;
X
X signal S3 : REAL;
X type T is (A);
X attribute A1 of all : type is 29741;
X type T5 is range -1.0 to 1.0;
Xbegin
X S3 <= C2'TC1;
X -- ERROR : declaration of C2 does not precede attribute specification
X S2 <= T5'A1;
X -- ERROR : declaration of T5 does not precede attribute specificati
X S4 <= T2'A1;
X -- ERROR : declaration of T2 not in same declarative part as
X -- attribute specification
X-- end block BB;
Xend ABB;
*-*-END-of-e-05-1-0-0010a.vhdl-*-*
echo x - e-05-1-0-0011a.vhdl
sed 's/^X//' >e-05-1-0-0011a.vhdl <<'*-*-END-of-e-05-1-0-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that no more than one attribute specification is allowed for any one
X-- attribute of any one entity. As a special case check that an attribute
X-- specification which specifies an alias counts as the one permitted attribute
X-- for the corresponding entity. As a special case check that an attribute
X-- specification with no entity name list must not follow within the same
X-- declarative part any attribute specification, with or without a name list,
X-- for the same entity class.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (PT:BOOLEAN) ;
X attribute A1 : REAL;
X type T1 is range 1 to 100000000 ;
X alias APT : BOOLEAN is PT;
X attribute A1 of PT : signal is 5.0;
X attribute A1 of PT : signal is 8.0;
X -- ERROR : no more than one attribute specification is allowed for any one
X -- entity and attribute
X attribute A1 of APT : signal is 5.0;
X -- ERROR: Attribute already specified
Xend E1;
X
Xuse P.all ;
Xpackage P is
X function F return TIME ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xfunction F return TIME is
X variable V1 : INTEGER;
X attribute A1 : INTEGER;
X alias AV1 : INTEGER is V1;
X attribute A1 of V1 : variable is 9;
X variable V2 : INTEGER;
X attribute A1 of v2 : variable is 10;
X attribute A1 of all : variable is 9258;
X -- ERROR : no more than one attribute specification is allowed for any one
X -- entity and attribute
Xbegin
X return 0 ns;
X end F;
Xend P ;
X
Xentity E1 is
X port (PT:BOOLEAN) ;
X attribute A1 : REAL;
Xend E1;
X
Xarchitecture AB of E1 is
X-- L_X_1:block
X attribute A1 of GUARD : signal is 6.0;
X attribute A1 of all : signal is 7.0;
X -- ERROR : no more than one attribute specification is allowed for any one
X -- entity and attribute
Xbegin
X process
X begin
X null;
X end process;
X-- end block;
Xend AB;
X
*-*-END-of-e-05-1-0-0011a.vhdl-*-*
echo x - e-05-1-0-0012a.vhdl
sed 's/^X//' >e-05-1-0-0012a.vhdl <<'*-*-END-of-e-05-1-0-0012a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0012A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a design entity can appear only
X-- immediatly within the declarative region of an interface declaration.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P1 is
X attribute A1 : REAL;
X function F1 return BOOLEAN ;
Xend P1;
X
X-- with package P1;
Xuse P1.all;
Xpackage body P1 is
Xfunction F1 return BOOLEAN is
X attribute A1 of P1 : package is 6.0;
X -- ERROR : attribute specification not in named design entity
X begin
X return FALSE;
Xend F1;
Xend P1 ;
X
Xuse P1.all ;
Xpackage body P1 is
Xfunction F1 return BOOLEAN is
X begin
X return FALSE;
Xend F1;
Xend P1 ;
X
X-- with package P1;
X-- with function F1;
Xuse P1.F1;
Xpackage P2 is
X attribute A1 of F1 : function is 7.0;
X -- ERROR : attribute specification not in named design entity
Xend P2;
*-*-END-of-e-05-1-0-0012a.vhdl-*-*
echo x - e-05-1-0-0013a.vhdl
sed 's/^X//' >e-05-1-0-0013a.vhdl <<'*-*-END-of-e-05-1-0-0013a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0013A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a body can appear only immediatly
X-- within the declarative part of a body declaration. As a special case
X-- check for attribute specifications for attributes of entity class body in
X-- the declarative part of the body's outermost block statement and of the
X-- associated interface declaration.
X-- NOTE : That is, check that there is currently no legal placement for
X-- attribute of bodies.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X attribute A1 : CHARACTER;
Xend P;
X
X-- with package P;
Xuse P.all;
Xpackage P is
Xfunction F1 return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 return BOOLEAN is
X attribute A1 of all : entity is '5';
X -- ERROR : entity attribute specification permitted only in entity
X -- declarative part
Xbegin
X return FALSE;
Xend F1 ;
Xend P ;
X
X-- with package P;
Xuse P.all;
Xentity E1 is
X attribute A1 of all : package is '8';
X -- ERROR : package attribute specification permitted only in package
X -- declarative part
Xend E1 ;
X
Xarchitecture ABC of E1 is
X-- BB : block
X attribute A1 of all : package is 'Z';
X -- ERROR : package attribute specification permitted only immediately within
X -- package declarative part.
X signal S1 : BOOLEAN;
X begin
X S1 <= FALSE;
X-- end block BB;
Xend ABC;
*-*-END-of-e-05-1-0-0013a.vhdl-*-*
echo x - e-05-1-0-0014a.vhdl
sed 's/^X//' >e-05-1-0-0014a.vhdl <<'*-*-END-of-e-05-1-0-0014a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0014A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a package can appear only
X-- immediately within the declarative part of a package declaration.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X attribute A1 : INTEGER;
X function F1 return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 return BOOLEAN is
X attribute A1 of P : package is 8;
X -- ERROR: package attribute specification can appear only immediatly
X -- within the declarative region of a package.
X begin
X return FALSE;
Xend F1 ;
Xend P;
X
Xpackage P is
X attribute A1 : INTEGER;
X function F1 return BOOLEAN ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
Xfunction F1 return BOOLEAN is
X begin
X return FALSE;
Xend F1 ;
Xend P;
X
X-- with package p;
XUse P.all;
Xentity E1 is
X attribute A1 of P : package is 9 ;
X -- ERROR: package attribute specification can appear only immediatly
X -- within the declarative region of a package.
Xend E1 ;
X
X-- with package p;
XUse P.all;
Xentity E1 is
Xend E1 ;
X
Xarchitecture ABC of E1 is
X-- BD : block
X attribute A1 of P : package is 9 ;
X -- ERROR: package attribute specification can appear only immediatly
X -- within the declarative region of a package.
X signal S1 : BOOLEAN;
X begin
X S1 <= FALSE;
X-- end block BD ;
Xend ABC ;
*-*-END-of-e-05-1-0-0014a.vhdl-*-*
echo x - e-05-1-0-0015a.vhdl
sed 's/^X//' >e-05-1-0-0015a.vhdl <<'*-*-END-of-e-05-1-0-0015a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0015A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a subprogram can appear only
X-- immediately within the declarative region of a subprogram declaration
X-- even when the subprogram is declared inside a package.
X-- JB (DB 7/15/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X attribute A1 : INTEGER;
X function F2 return BOOLEAN ;
X attribute A1 of all : function is 5;
X -- ERROR : an attribute of subprogram can only appear in a subprogram
X -- declarative region.
X procedure P1 ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F2 return BOOLEAN is
X begin
X return FALSE;
X end F2;
Xprocedure P1 is
Xbegin
X null;
Xend P1;
Xend P;
X
Xuse P.all ;
Xpackage P is
X attribute A1 : INTEGER;
X function F2 return BOOLEAN ;
X procedure P1 ;
Xend P;
X
Xuse P.all ;
Xpackage body P is
X function F2 return BOOLEAN is
X begin
X return FALSE;
X end F2;
X procedure P1 is
Xbegin
X null;
Xend P1;
Xend P;
X
X-- with package P;
Xuse P.all;
Xentity E1 is
X attribute A1 of all : procedure is 5;
X -- ERROR : an attribute of subprogram can only appear in a subprogram
X -- declarative region.
Xend E1;
X
X-- with package P;
Xuse P.all;
Xentity E1 is
Xend E1;
X
Xarchitecture ABD of E1 is
X-- BB : block
X attribute A1 of all : function is 5;
X -- ERROR : an attribute of subprogram can only appear in a subprogram
X -- declarative region.
Xbegin
X process
X attribute A1 of all : procedure is 5;
X -- ERROR : an attribute of subprogram can only appear in a subprogram
X -- declarative region.
X begin
X null;
X end process;
X-- end block BB;
Xend ABD;
*-*-END-of-e-05-1-0-0015a.vhdl-*-*
echo x - e-05-1-0-0016a.vhdl
sed 's/^X//' >e-05-1-0-0016a.vhdl <<'*-*-END-of-e-05-1-0-0016a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0016A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a type, port, signal, variable,
X-- constant or labeled entity can appear only immediately within a declarative
X-- part where a preceding declaration of an entity of the specified entity class
X-- appears. As a special case check that such an attribute specification is not
X-- permitted in a declarative part when there is no such preceding entity
X-- declaration.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X-- attribute A1 of type, port, signal, variable, constant, label is REAL;
X attribute A1 : REAL;
X attribute A1 of all : variable is 7.0;
X -- ERROR : variable declarations not permitted in this declarative part
X attribute A1 of all : signal is 7.0;
X -- ERROR : signal declarations not permitted in this declarative part
X attribute A1 of all : constant is 7.0;
X -- ERROR : constant declarations not permitted in this declarative part
X attribute A1 of all : label is 7.0;
X -- ERROR : label declarations cannot be implied in this declarative part
Xend P;
X
Xuse P.all ;
Xpackage P is
X attribute A1 : REAL;
Xend P;
X
X-- with package P;
Xuse P.all;
Xentity E is
X attribute A1 of all : signal is 7.0;
X -- ERROR : Attribute specification is not meaningful in this context,
X -- No port signals are visible
X attribute A1 of all : type is 9.0;
X -- ERROR : Attribute specification is not meaningful in this context,
X -- No Type are available for specification.
Xend E;
X
X-- with package P;
Xuse P.all;
Xentity E is
Xend E;
X
Xarchitecture ABC of E is
X-- BB : block
X signal S1 : bit;
X begin
X B2 : block
X attribute A1 of B2 : label is 6.0;
X -- ERROR : Label must specified in the declarative part where it is declared
X
X attribute A1 of S1 : signal is 7.0;
X -- ERROR : Signal must specified in the declarative part where the object
X -- is declared
X begin
X process begin null; end process;
X end block;
X
X B3 : block
X signal S5 : bit;
X attribute A1 of all : label is 66.0;
X -- ERROR: Attribute specification is not meaningful in this context
X -- Not labels are decl'd in this declarative part.
X begin
X S5 <= '0';
X end block B3;
X P1: process
X begin null; end process P1;
X-- end block BB;
Xend ABC;
*-*-END-of-e-05-1-0-0016a.vhdl-*-*
echo x - e-05-1-0-0016b.vhdl
sed 's/^X//' >e-05-1-0-0016b.vhdl <<'*-*-END-of-e-05-1-0-0016b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0016B.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an attribute specification for a type, port, signal, variable,
X-- constant or labeled entity can appear only immediately within a declarative
X-- part where a preceding declaration of an entity of the specified entity class
X-- appears. As a special case check that such an attribute specification is not
X-- permitted in a declarative part when there is no such preceding entity
X-- declaration.
X-- DB 7/17/85
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X-- attribute A1 of type, port, signal, variable, constant, label is REAL;
X attribute A1 : REAL;
Xend P;
X
X-- with package P;
Xuse P.all;
Xentity E1 is
X attribute A1 of all : type is 7.0;
X -- ERROR : no type declarations precede the attribute specification
X attribute A1 of all : signal is 7.0;
X -- ERROR : no port declarations are implied in this declarative part
X attribute A1 of all : constant is 7.0;
X -- ERROR : no constant declarations precede the attribute specification
Xend E1;
X
Xarchitecture AB of E1 is
X-- L_X_1:block
X attribute A1 of all : label is 7.0;
X -- ERROR : no label declarations are implied in this declarative part
Xbegin
X process
X attribute A1 of all : variable is 7.0;
X -- ERROR : no variable declarations precede the attribute specification
X begin
X null;
X end process;
X-- end block;
Xend AB;
*-*-END-of-e-05-1-0-0016b.vhdl-*-*
echo x - e-05-1-0-0017a.vhdl
sed 's/^X//' >e-05-1-0-0017a.vhdl <<'*-*-END-of-e-05-1-0-0017a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-1-0017A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that references to undefined attributes are not permitted.
X-- That is, check that both the attribute declaration and an attribute
X-- specification must precede all references to that attribute.
X-- JB (DB 7/17/85)
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X attribute A1 of all : entity is 6;
X -- ERROR : attribute used is not declared.
Xend E;
X
Xentity E is
Xend E;
X
Xarchitecture AB of E is
X-- B : block
X attribute A3 : INTEGER;
X attribute A2 of all : signal is FALSE ;
X -- ERROR : attribute used has not been defined.
X attribute A2 : BOOLEAN;
X signal S1,S2 : INTEGER;
Xbegin
X S1 <= S1'A2;
X -- ERROR : no attribute specification for this entity
X-- end block B;
Xend AB;
*-*-END-of-e-05-1-0-0017a.vhdl-*-*
echo x - e-05-2-0-0001a.vhdl
sed 's/^X//' >e-05-2-0-0001a.vhdl <<'*-*-END-of-e-05-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an application specification in an architecture body must
X-- not be a block statement label.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT is
Xend ENT;
X
Xarchitecture AB of ENT is
Xbegin
X C : block
X signal B : BOOLEAN;
X for C : foo_comp -- ERROR: Application specification in an architecture body
X -- must not be block statement label.
X use open ;
X-- end for;
X begin
X B <= true;
X end block C;
Xend AB;
X
*-*-END-of-e-05-2-0-0001a.vhdl-*-*
echo x - e-05-2-0-0002a.vhdl
sed 's/^X//' >e-05-2-0-0002a.vhdl <<'*-*-END-of-e-05-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that configuration specification in architecture bodies must contain
X-- a binding indication and that there are no next level configurations.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E0 is
X port (b : in bit) ;
Xend E0;
X
Xentity E is
X port (pt : Boolean) ;
Xend E;
X
Xarchitecture AB of E is
X-- D : block
X component LOCAL port ( CI : in Bit);
X end component ;
X constant b : boolean := False;
X
X for ALL : LOCAL
X -- ERROR : missing binding_indication
X type T1 is range 1 to 2;
X -- ERROR: next level configurations are not allowed in an
X -- architecture block
X-- end for;
X begin
X process begin null; end process;
X-- end block;
Xend AB;
X
*-*-END-of-e-05-2-0-0002a.vhdl-*-*
echo x - e-05-2-0-0003a.vhdl
sed 's/^X//' >e-05-2-0-0003a.vhdl <<'*-*-END-of-e-05-2-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a binding indication is not permitted in a configuration
X-- specification which define the configuration of a block
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity E0 is
Xend E0;
X
Xentity ENT is
Xend ENT;
X
Xarchitecture AB of ENT is
Xbegin
XDE : block
X signal S1 : BOOLEAN;
X begin
X S1 <= true;
Xend block DE;
Xend AB;
X
X
X-- configuration ONE of ENT for AB is
Xconfiguration ONE of ENT
X--for AB
X is
X --block configuration
X for AB
X for DE use
X -- ERROR: binding indications are not allowed in a configuration of a block
X-- entity (E0) architecture(open); -- 7.2
X entity E0 open; -- 1076
X end for;
Xend ONE;
X
*-*-END-of-e-05-2-0-0003a.vhdl-*-*
echo x - e-05-2-0-0004a.vhdl
sed 's/^X//' >e-05-2-0-0004a.vhdl <<'*-*-END-of-e-05-2-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that labels in an instantion list must exist in the related declaraive
X-- region and must correspond to instantiations of the given component.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage types is
X type bit_array is array (1 to 32) of bit;
Xend types;
X
X-- with package types;
Xuse types.all;
Xentity E_lib is
X port (a: boolean; b : boolean; reg : bit_array) ;
Xend E_lib;
X
X
X-- with package types;
Xuse types.all;
Xentity E is
X generic (bar : bit_array) ;
X port (PT1, pt2 : BOOLEAN; pt3 : bit_array) ;
Xend E;
X
Xarchitecture AB of E is
Xbegin
X BB : block
X component FOUR
X port (a: boolean; b : boolean; reg : bit_array);
X end component ;
X begin
X LA : FOUR port map (pt1, pt2, pt3);
X LC : FOUR port map (pt1, pt2, pt3);
X end block BB;
Xend AB;
X
Xconfiguration ONE of E is
Xfor AB
X for BB
X for LB : Four
X -- ERROR: label LB is not defined in the related declarative region.
X use
X-- entity (E_lib)
X-- architecture(Open);
X open ;
X end for;
X
X for LD : Four
X -- ERROR: label LB is not defined in the related declarative region.
X use
X-- entity E_lib open ;
X-- architecture(Open);
X open ;
X end for;
X end for;
Xend for;
Xend ONE;
*-*-END-of-e-05-2-0-0004a.vhdl-*-*
echo x - e-05-2-0-0005a.vhdl
sed 's/^X//' >e-05-2-0-0005a.vhdl <<'*-*-END-of-e-05-2-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in a given design unit, no more than one configuration
X-- specification is permitted to define the same component instance or
X-- block statement.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity FE is
Xend FE;
X
Xentity ETY is
Xend ETY;
X
Xarchitecture AB of ETY is
Xbegin
X BB : block
X component ET
X end component ;
X for LA : ET
X use
X-- entity (FE)
X-- architecture( open);
X open ;
X-- end for;
X for LA : ET
X --ERROR: in a given design unit no more than one configuration
X -- specification is permitted to define the same component instance.
X use
X-- entity (FE)
X-- architecture(Open);
X open ;
X-- end for;
X begin
X LA : ET;
X LB : ET ;
X end block;
Xend AB;
X
Xarchitecture AB of ETY is
Xbegin
X BB : block
X component ET
X end component ;
X for LA : ET
X use
X-- entity (FE)
X-- architecture( open);
X open ;
X-- end for;
X begin
X LA : ET;
X LB : ET;
X end block;
Xend AB;
X
X
Xconfiguration ONE of ETY is
Xfor AB
X for BB
X for LA : ET
X --ERROR: in a given design unit no more than one configuration
X -- specification is permitted to define the same component instance.
X use
X-- entity (FE)
X-- architecture(open);
X open ;
X end for;
X end for;
Xend for ;
Xend ONE;
*-*-END-of-e-05-2-0-0005a.vhdl-*-*
echo x - e-05-2-0-0007a.vhdl
sed 's/^X//' >e-05-2-0-0007a.vhdl <<'*-*-END-of-e-05-2-0-0007a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0007A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an application specification with no component simple name must
X-- consist of a block statement label which is implicitly declared in the
X-- declarative region related to the corresponding next level configuration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity H is
Xend H;
X
Xentity ENT is
X port ( PT : Boolean ) ;
Xend ENT ;
X
Xarchitecture ABD of ENT is
Xbegin
X BD : block
X component comp1
X end component ;
X begin
X CIS : comp1;
X BD_nested : block
X begin
X process
X begin
X null;
X End process;
X end block;
X end block BD ;
Xend ABD ;
X
Xconfiguration ONE of ENT is
Xfor ABD
X for CIS
X -- ERROR: the CIS is not a declared block in the declarative region.
X-- Type T1 is range 1 to 50 ;
X end for ;
X for BD_nested
X -- ERROR :: BD_nested is not a block label in the related declarative region.
X-- type f is (u, two);
X end for;
X end for;
Xend ONE ;
*-*-END-of-e-05-2-0-0007a.vhdl-*-*
echo x - e-05-2-0-0008a.vhdl
sed 's/^X//' >e-05-2-0-0008a.vhdl <<'*-*-END-of-e-05-2-0-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a Configuration specification with binding indication in
X-- a configuration body must not configure a component instance which is
X-- also configured in the corresponding architectureal body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EG0 is
X port (i : integer) ;
Xend EG0;
X
Xarchitecture EG_bod of EG0 is
Xbegin
Xpp: block
X signal s1 : bit;
X begin
X s1 <= '0';
X end block;
Xend EG_bod;
X
Xentity kk is
Xend KK;
X
Xarchitecture ll of KK is
Xbegin
XGH: block
X signal g1 : integer;
X component hat port (y : integer);
X end component ;
X for L1 : hat use entity EG0 (EG_bod)
X port map (i => y) ;
X-- end for;
X begin
X L1 : hat port map (y => g1);
X end block;
Xend ll;
X
Xconfiguration CV of KK is
Xfor ll
X for GH
X for L1: hat use
X -- ERROR: Instance is already configured in related region
X entity EG0 (EG_bod)
X port map (i => y);
X end for;
X end for ;
Xend for;
Xend;
X
*-*-END-of-e-05-2-0-0008a.vhdl-*-*
echo x - e-05-2-1-1001a.vhdl
sed 's/^X//' >e-05-2-1-1001a.vhdl <<'*-*-END-of-e-05-2-1-1001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1101A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the entity indication of an entity aspect must not be empty
X-- i.e. no empty parenthesis.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ENT is
X generic (k2 : integer) ;
X port (shift : boolean;
X ran : integer;
X S1 : bit ) ;
X
Xend;
X
Xarchitecture ABC of ENT is
Xbegin
X BB : block
X component FR
X generic (k : integer);
X port (i : boolean;
X j : integer;
X b : bit) ;
X end component ;
X begin
X LA : FR generic map (k => k2)
X port map (i => SHIFT, j => RAN, b => S1) ;
X end block;
Xend ABC;
X
Xconfiguration ONE of ENT is
Xfor ABC
X for BB
X for LA : FR
X use entity open;
X-- ERROR: entity indication of an entity must not be empty
X-- architecture(open);
X end for;
X end for;
Xend for;
Xend ONE;
*-*-END-of-e-05-2-1-1001a.vhdl-*-*
echo x - e-05-2-1-1002a.vhdl
sed 's/^X//' >e-05-2-1-1002a.vhdl <<'*-*-END-of-e-05-2-1-1002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1102A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if the entity aspect is "open" then the port map aspect, the
X-- generic aspect, the actual ports aspect, and the actual generics aspect
X-- are not permitted and the body indication of the body aspect must also be
X-- "open".
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ALU is end;
X
Xarchitecture CYC of ALU is
Xbegin
XBB:block
X component FR
X end component ;
X begin
X LA : FR;
X end block;
Xend;
X
Xentity E5 is end;
X
Xarchitecture B5 of E5 is
Xbegin
XBB5:block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xconfiguration ONE of ALU is
Xfor CYC
X for BB
X for LA : FR
X use
X-- entity OPEN (B5);
X OPEN
X -- ERROR: IF entity is open then the body must be open
X generic map (NO_OF_ADDERS => k)
X -- ERROR: If entity is open the generic map aspect is not permitted
X-- generic ( NOA => K2)
X-- -- ERROR: If entity is open the generic aspect is not permitted
X port map (p => i, p2 => j)
X -- ERROR: If entity is open the port map aspect is not permitted
X-- port ( A => S1)
X-- -- ERROR: If entity is open the port aspect is not permitted
X ;
X end for;
X end for;
X end for;
Xend ONE;
*-*-END-of-e-05-2-1-1002a.vhdl-*-*
echo x - e-05-2-1-1003a.vhdl
sed 's/^X//' >e-05-2-1-1003a.vhdl <<'*-*-END-of-e-05-2-1-1003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1401A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if the entity aspect implies a particular design entity then the
X-- body aspect must not imply a library name which is not a body of the specified
X-- kind associated with the design entity implied by the entity aspect.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture AA of E is
Xbegin
X AB : block
X begin
X process begin null; end process;
X end block;
Xend;
X
X
Xentity ALU is
Xend ALU ;
X
Xarchitecture CYC of ALU is
Xbegin
X B : block
X component B1
X end component ;
X begin
X L1 : B1;
X end block B ;
Xend CYC ;
X
Xarchitecture LYL of ALU is
Xbegin
X CD : block
X component C2
X end component ;
X begin
X L2 : C2;
X end block CD ;
Xend LYL ;
X
Xconfiguration ONETRY of ALU is
Xfor CYC
X for B
X for all : B1
X use
X entity E (CYC) ;
X -- ERROR: Architecture CYC is not a body of entity E;
X end for ;
X end for;
Xend for;
Xend ONETRY ;
X
Xconfiguration SECONDTRY of ALU is
X for LYL
X for CD
X for all : C2
X use
X entity ALU ( AA ) ;
X -- ERROR: Design Unit AA is not a body of interface ALU
X end for ;
X end for;
Xend for;
Xend SECONDTRY ;
X
*-*-END-of-e-05-2-1-1003a.vhdl-*-*
echo x - e-05-2-1-2002a.vhdl
sed 's/^X//' >e-05-2-1-2002a.vhdl <<'*-*-END-of-e-05-2-1-2002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1202A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that each interface element from the component declaration must be
X-- as an actual designator and associated with at least one element from
X-- the corresponding design entity.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity MBA is
X generic ( NOA, NOB : Integer) ;
X port ( A, B : in Bit ;
X CIN : in Bit ;
X SUM : out Bit ;
X COUT : OUT Bit) ;
Xend MBA;
X
Xarchitecture AA of MBA is
Xbegin
X AAB : block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xentity EW is
Xend EW;
X
Xarchitecture RS of EW is
Xbegin
X BB : block
X signal S1 : BIT;
X component LA port(C1,C2,C3 : in Bit ;
X S2 : out Bit);
X end component ;
X for ALL : LA
X use
X entity MBA ( AA )
X port map ( A => C1, B => C2, COUT => S2)
X -- ERROR: component element C3 is not associated with an element from
X -- the corresponding design entity.
X ;
X-- end for;
X begin
X S1 <= '1';
X end block BB;
Xend RS;
*-*-END-of-e-05-2-1-2002a.vhdl-*-*
echo x - e-05-2-1-2003a.vhdl
sed 's/^X//' >e-05-2-1-2003a.vhdl <<'*-*-END-of-e-05-2-1-2003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1203A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that it is not permitted for any interface element from the
X-- corresponding design entity to be used as a formal designator associated
X-- with more than one interface element from the component declaration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity MBA is
X generic (NOA, NOB : Integer ) ;
X port (A,B : in Bit ;
X SUM : out Bit ;
X COUT : out Bit) ;
X
Xend MBA ;
X
Xentity EW is
Xend EW;
X
Xarchitecture RS of EW is
Xbegin
X BB : block
X signal S1 : integer;
X component LA
X generic (GNA, GNB : Integer );
X port ( CI, CII, C3 : in Bit;
X CO : out Bit);
X end component ;
X for all : LA
X use
X entity MBA
X generic map ( NOA => GNA, NOB => GNB )
X port map ( A => CI, A => CII, B => C3, COUT => CO)
X -- ERROR : A cannot go to more than one interface element from the
X -- component declaration.
X-- architecture(open);
X ;
X-- end for;
X begin
X S1 <= 1;
X end block BB;
Xend RS;
*-*-END-of-e-05-2-1-2003a.vhdl-*-*
echo x - e-05-2-1-2004a.vhdl
sed 's/^X//' >e-05-2-1-2004a.vhdl <<'*-*-END-of-e-05-2-1-2004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1204A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the mode of each interface element from the component
X-- declaration used as an actual designator must match the mode
X-- of the associated interface element from the corresponding design
X-- entity.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EMT is
X generic ( NOA, NOB : Integer ) ;
X port ( A : in Bit ;
X COUT : out Bit ) ;
Xend EMT;
X
Xarchitecture AA of EMT is
Xbegin
X BB :block
X signal S1 : Integer;
X begin
X S1 <= 1;
X end block;
Xend;
X
Xentity ET is
Xend ET;
X
X
Xarchitecture ABC of ET is
Xbegin
X BB : block
X signal S1 : Integer;
X signal SUM,B : BIT;
X component LA
X generic ( SNOA : Integer ; SNOB : Integer );
X port( SA : out Bit;
X SSUM : inout Bit) ;
X end component ;
X for all : LA
X use
X entity EMT ( AA )
X generic map ( NOA => SNOA , NOB => SNOB)
X port map ( A => SA,
X -- ERROR: the mode of actual from the component declaration must match
X -- the mode from the interface element.
X COUT => SSUM)
X -- ERROR: the mode of actual from the component declaration must match
X -- the mode from the interface element.
X ;
X-- end for;
X begin
X L : LA generic map (SNOA => 1, SNOB => 2)
X port map (SA => B, SSUM => SUM) ;
X S1 <= 1;
X end block BB;
Xend ABC;
X
*-*-END-of-e-05-2-1-2004a.vhdl-*-*
echo x - e-05-2-1-2005a.vhdl
sed 's/^X//' >e-05-2-1-2005a.vhdl <<'*-*-END-of-e-05-2-1-2005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1205A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that when the binding indication is defaulted the corresponding design
X-- entity must have a port of the same name as each port in the component
X-- declaration and a generic of the same name as each generic in the
X-- component declaration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity EBT is
X generic (NOA , NOB : Integer ) ;
X port (A,B : in Bit ;
X CIN : in Bit ) ;
X
Xend EBT;
X
Xentity ET is
Xend ET;
X
Xarchitecture ABC of ET is
Xbegin
X BB : block
X signal S1 : BOOLEAN ;
X component LA
X generic ( NOA , NOD : Integer );
X port ( A, D : in Bit ;
X CIN : inout Bit ) ;
X end component ;
X for all : LA
X use
X entity EBT ( MIX );
X-- end for;
X-- ERROR: when binding indication is defaulted the corresponding port and
X-- generic elements in the component declaration must be the same as
X-- the interface list.
X begin
X S1 <= false;
X end block BB;
Xend ABC;
*-*-END-of-e-05-2-1-2005a.vhdl-*-*
echo x - s-05-1-0-0001a.vhdl
sed 's/^X//' >s-05-1-0-0001a.vhdl <<'*-*-END-of-s-05-1-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-1-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the entity name list in an entity specification is optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EZ is
Xend EZ;
X
Xarchitecture ABC of EZ is
Xbegin
X BD : block
X
X type T1 is range 1 to 2 ;
X type T2 is range 2 to 10000 ;
X
X attribute A : integer ;
X attribute A of all : type is 5;
X
X begin
X P1 : process
X variable B : boolean;
X begin
X if T1'A = 5 then
X B := TRUE;
X end if;
X end process;
X end block BD ;
Xend ABC ;
*-*-END-of-s-05-1-0-0001a.vhdl-*-*
echo x - s-05-1-0-0002a.vhdl
sed 's/^X//' >s-05-1-0-0002a.vhdl <<'*-*-END-of-s-05-1-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-1-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that attribute specification are permitted for all user-defined
X-- attributes.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X attribute A : integer ;
X attribute A of P : package is 2;
X
X constant C1 : integer := 5 ;
X attribute TC1 : integer ;
X attribute TC1 of C1 : constant is 8 ;
X
X attribute A1 : integer ;
X
X function F1 return boolean ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
X function F1 return boolean is
X attribute A1 of F1 : function is 8;
X begin
X return False;
X end F1;
X
Xend P ;
X
Xentity E1 is
X port (PA : bit) ;
X
X attribute AE1 : boolean ;
X attribute AE1 of E1 : entity is TRUE;
X
X type T1 is range 1 to 190 ;
X attribute TT1 : integer ;
X attribute TT1 of T1 : type is 25 ;
X
X attribute A1 : Integer ;
X attribute A1 of PA : signal is 6 ;
X
Xend E1 ;
X
Xuse P.all ;
Xpackage P is
Xprocedure P3 ;
Xend P ;
X
Xuse P.all ;
Xpackage body P is
Xprocedure P3 is
X
X attribute P4 : Boolean ;
X attribute P4 of P3 : procedure is False ;
X
X variable V2 : Integer ;
X attribute VA : integer ;
X attribute VA of V2 : variable is 5 ;
X begin
X null ;
Xend P3 ;
Xend P ;
X
Xarchitecture ABC of E1 is
Xbegin
X BD : block
X
X attribute LA : Boolean ;
X attribute LA of BL2 : label is false ;
X
X signal S1 : Boolean ;
X attribute TS1 : boolean ;
X attribute TS1 of S1 : signal is true ;
X
X begin
X BL2 : block
X begin
X process
X begin
X null;
X end process;
X end block;
X S1 <= false ;
X end block BD ;
Xend ABC ;
X
*-*-END-of-s-05-1-0-0002a.vhdl-*-*
echo x - s-05-1-0-0003a.vhdl
sed 's/^X//' >s-05-1-0-0003a.vhdl <<'*-*-END-of-s-05-1-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: File: %P%
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Original file name: S-05-1-1-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that attribute specification for attributes of entities which may
X-- be design units may appear in any number of declarations for design units
X-- of the specified entity class as long as each has entity name list.
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Steve)Grout@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xpackage P is
X attribute A1 : Integer;
Xend P;
X
X-- with package p;
Xuse p.all ;
Xpackage P is
X function F1 return boolean ;
Xend P ;
X
Xuse p.all ;
Xpackage body P is
X function F1 return boolean is
X attribute A1 of F1 : function is 8 ;
X begin
X return false ;
X end F1 ;
Xend P ;
X
Xuse p.all;
Xpackage P is
X function F2 return boolean ;
Xend P ;
X
Xuse p.all;
Xpackage body P is
X function F2 return boolean is
X attribute A1 of F2 : function is 3 ;
X begin
X return false ;
Xend F2 ;
Xend P ;
X
Xuse p.all;
Xpackage P is
X function F3 return boolean ;
Xend P ;
X
Xuse p.all;
Xpackage body P is
X function F3 return boolean is
X attribute A1 of F3 : function is 2 ;
X begin
X return false ;
Xend F3 ;
Xend P ;
X
X
X-- with package p;
Xuse p.all;
Xpackage P is
X function F4 return boolean ;
Xend P ;
X
Xuse p.all;
Xpackage body P is
X function F4 return boolean is
X attribute A1 of F4 : function is 9 ;
X begin
X return false ;
Xend F4 ;
Xend P ;
X
X-- with package p;
Xuse p.all;
Xpackage P is
X function F5 return boolean ;
Xend P;
X
Xuse p.all;
Xpackage body P is
X function F5 return boolean is
X attribute A1 of F5 : function is 8 ;
X begin
X return false ;
Xend F5 ;
Xend P;
X
X-- with package p;
Xuse p.all ;
Xpackage P is
X function F6 return boolean ;
Xend P ;
X
Xuse p.all ;
Xpackage body P is
X function F6 return boolean is
X attribute A1 of F6 : function is 8 ;
X begin
X return false ;
Xend F6 ;
Xend P ;
X
*-*-END-of-s-05-1-0-0003a.vhdl-*-*
echo x - s-05-1-0-0004a.vhdl
sed 's/^X//' >s-05-1-0-0004a.vhdl <<'*-*-END-of-s-05-1-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-1-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that an entity inherits an attribute if the declaration
X-- of the entity preceeds within the same declarative region or encloses
X-- an attribute specification for that attribute which either includes that
X-- entity in its entity name list or has no entity name list but specifies
X-- that entity's entity class.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage H is
X attribute A2_specific : boolean;
X attribute A2_general : boolean;
X
X function F1(t : boolean) return bit ;
X function F2(t : boolean) return bit ;
Xend H;
X
Xuse H.all ;
Xpackage body H is
X function F1(t : boolean) return bit is
X attribute A2_specific of F1 : function is False;
X variable V_bit : bit;
X begin
X return V_bit;
X end F1;
X
X function F2(t : boolean) return bit is
X attribute A2_general of all : function is False ;
X variable V_bit : bit;
X begin
X return V_bit;
X end F2;
Xend H;
X
X-- with package H;
Xuse H.all;
Xentity C is
Xend c;
X
Xarchitecture D of C is
Xbegin
XBB: block
X attribute A_specific : integer ;
X attribute A_general : integer ;
X
X type T1 is range 1 to 4;
X attribute A_specific of T1 : type is 1;
X
X type T2 is range 1 to 4;
X attribute A_general of all : type is 6;
X begin
X process
X variable Always_true : boolean range True to True;
X variable B1, B2 : boolean;
X attribute A_specific of B1 : variable is 3;
X attribute A_general of all : variable is 7;
X begin
X case Always_true is when ( T2'A_general = 6 ) => null; end case;
X case Always_true is when ( B2'A_general = 7 ) => null; end case;
X case Always_true is when not F2'A2_general => null; end case;
X case Always_true is when not F1'A2_specific => null; end case;
X
X return;
X end process;
X end block;
Xend D;
*-*-END-of-s-05-1-0-0004a.vhdl-*-*
echo x - s-05-1-0-0005a.vhdl
sed 's/^X//' >s-05-1-0-0005a.vhdl <<'*-*-END-of-s-05-1-0-0005a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-1-0005A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that all names which denote an object associated with an attribute
X-- may be used as a prefix of that attribute in an attribute name.
X-- As a special case, check for aliases declared after the attribute
X-- specification and also for attribute specifications which specify the
X-- alias name.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xpackage JJ is
X-- 7.2 attribute M of variable, constant, port, signal is severity_level;
X attribute M : severity_level; -- 1076
Xend JJ;
X
X-- with package JJ;
XUse JJ.all;
Xentity II is
X port (p1 : bit) ;
X constant C1 : boolean := TRUE;
X alias C1_too : boolean is C1;
X alias p1_too : bit is p1;
X
X attribute M of C1_too : constant is warning;
X attribute M of P1_too : signal is note;
X
Xend II;
X
Xuse JJ.all ;
Xarchitecture AA of II is
Xbegin
XKK: block
X signal S1 : bit;
X alias S1_too : bit is S1;
X attribute M of S1 : signal is note;
X begin
X O: process
X variable Always_true : boolean range True to True;
X begin
X case Always_true is when ( p1'M = note ) => null; end case;
X case Always_true is when ( C1'M = warning ) => null; end case;
X case Always_true is when ( s1_too'M = note ) => null; end case;
X end process;
X end block;
Xend AA;
X
X-- with package JJ;
XUse JJ.all;
Xpackage JJ is
Xfunction FOG(b : boolean) return integer ;
Xend JJ ;
X
XUse JJ.all;
Xpackage body JJ is
Xfunction FOG(b : boolean) return integer is
X variable Always_true : boolean range True to True;
X variable V1 : boolean;
X alias V1_too : boolean is V1;
X attribute M of V1 : variable is warning;
X begin
X case Always_true is when ( V1_too'M = warning ) => return 1 ; end case;
Xend FOG;
Xend JJ ;
*-*-END-of-s-05-1-0-0005a.vhdl-*-*
echo x - s-05-1-2-2001c.vhdl
sed 's/^X//' >s-05-1-2-2001c.vhdl <<'*-*-END-of-s-05-1-2-2001c.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-1301A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if an interface element from the interface declaration has a
X-- default value then association by a map aspect or an actual aspect is
X-- optional.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X entity EMP is
X port ( A : Integer := 1 ;
X B : in Bit ;
X C : in Boolean := true ) ;
X end EMP ;
X
Xentity EMT is
X port (sig : bit) ;
Xend EMT;
X
Xarchitecture ABC of EMT is
Xbegin
X BB : block
X component LA port ( S1 : Bit );
X end component;
X for all : LA
X use
X entity EMP -- architecture (open)
X port map (B => S1)
X -- port (A => 1, C => True) -- optional since interface has defaults
X-- end for;
X ;
X begin
X CIS1 : LA port map (S1 => sig);
X end block BB ;
Xend ABC ;
*-*-END-of-s-05-1-2-2001c.vhdl-*-*
echo x - s-05-2-0-0001a.vhdl
sed 's/^X//' >s-05-2-0-0001a.vhdl <<'*-*-END-of-s-05-2-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in configuration bodies binding indications are optional
X-- in configuration specification of component instances if there is either a
X-- select directive which applies to the corresponding next level consiguration
X-- or configuration specification for the given component instance in the
X-- corresponding architecture body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EZ is
X port (A : Bit ;
X B : inout Integer;
X C : out Integer) ;
Xend EZ;
X
Xarchitecture AZ of EZ is
Xbegin
X AZ_BLK : block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xentity EE is
X port (D2 : out Integer) ;
Xend EE;
X
Xarchitecture AB of EE is
Xbegin
X BB : block
X signal C1 : BIT;
X signal D1 : INTEGER;
X component FOUR port ( CONTROL : in bit;
X DATA_IN : inout integer;
X DATA_OUT : out integer);
X end component ;
X for MOST : FOUR
X use
X entity EZ (AZ)
X port map ( A => CONTROL ,B => DATA_IN, C => DATA_OUT )
X-- end for;
X ;
X begin
X Most : Four
X port map (Control => C1, Data_in => D1, Data_out => D2 );
X end block BB;
Xend AB;
X
Xconfiguration ONE of EE is
Xfor AB
X for BB
X for MOST : FOUR
X-- type I is range 1 to 1000;
X end for;
X end for;
Xend for ;
Xend ONE;
X
Xentity FOUR is
X port (CONTROL : in Bit;
X DATA_IN : inout Integer;
X DATA_OUT : out Integer) ;
Xend;
X
Xarchitecture FOURBODY of FOUR is
Xbegin
X FB : block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xarchitecture AB2 of EE is
Xbegin
X BB : block
X signal C1 : BIT;
X signal D1 : INTEGER;
X component FOUR port ( CONTROL : in bit;
X DATA_IN : inout integer;
X DATA_OUT : out integer);
X end component;
X begin
X Most : Four port map (Control => C1, Data_in => D1, Data_out => D2 );
X end block BB;
Xend AB2;
X
X-- the following test under 1076 is fairly gutless
X-- but is left in just for completeness. jsgrout
XConfiguration TWO of EE is
Xfor AB2
X for BB
X-- Select H; -- 7.2
X-- For Most : Four
X-- end For;
X end For;
Xend for ;
Xend Two;
X
*-*-END-of-s-05-2-0-0001a.vhdl-*-*
echo x - s-05-2-0-0002a.vhdl
sed 's/^X//' >s-05-2-0-0002a.vhdl <<'*-*-END-of-s-05-2-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a configuration specification in a configuration body may define
X-- the configuration of a block or instances of components.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E3 is
Xend E3;
X
Xarchitecture A2 of E3 is
Xbegin
X A2_BLK : block
X signal S1 : INTEGER;
X begin
X S1 <= 2;
X end block;
Xend A2;
X
Xentity ENT is
Xend ENT;
X
Xarchitecture ABC of ENT is
Xbegin
X DBLK : block
X component FOUR
X end component;
X begin
X LS : FOUR ;
X end block DBLK;
Xend ABC;
X
Xconfiguration ONE of ENT is
Xfor ABC
X for DBLK
X for LS : FOUR
X use
X entity E3 (A2);
X end for;
X end for;
Xend for ;
Xend ONE;
*-*-END-of-s-05-2-0-0002a.vhdl-*-*
echo x - s-05-2-0-0003a.vhdl
sed 's/^X//' >s-05-2-0-0003a.vhdl <<'*-*-END-of-s-05-2-0-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a configuration specification in an architecture body may
X-- configure component instances.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X port (ia, ib : bit;
X oc, od : out bit) ;
Xend E1;
X
Xarchitecture A1 of E1 is
Xbegin
X A1_BLK : block
X signal S : INTEGER;
X begin
X S <= 1;
X end block;
Xend A1;
X
Xentity EE is
X port (P3 : out bit;
X P4 : out bit) ;
Xend EE;
X
Xarchitecture AB of EE is
Xbegin
X BB : block
X signal S1 : bit;
X signal S2 : bit;
X component LOCAL port(CI, I2 : in BIT;
X CO, RES :out BIT);
X end component ;
X
X for all : LOCAL
X use
X entity E1 (A1)
X port map (ia => CI, ib => I2, oc => CO, od => RES)
X ;
X-- end for;
X begin
X L : LOCAL port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
X end block BB;
Xend AB;
*-*-END-of-s-05-2-0-0003a.vhdl-*-*
echo x - s-05-2-0-0004a.vhdl
sed 's/^X//' >s-05-2-0-0004a.vhdl <<'*-*-END-of-s-05-2-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that a configuration specification in a configuration body may
X-- contain both a binding indication and a next level configuration.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
Xend E1;
X
Xarchitecture A1 of E1 is
Xbegin
X A1_BLK : block
X signal S : INTEGER;
X begin
X S <= 1;
X end block;
Xend A1;
X
Xentity EE is
Xend EE;
X
Xarchitecture AA of EE is
Xbegin
X AA_BLK : block
X component FOUR
X end component;
X begin
X LH : FOUR;
X end block;
Xend AA;
X
Xconfiguration TWO of EE is
Xfor AA
X for AA_BLK
X for LH : FOUR
X use
X entity E1 (A1);
X-- type E is range 1.4 to 5000000.2;
X end for;
X end for;
X end for ;
Xend TWO;
*-*-END-of-s-05-2-0-0004a.vhdl-*-*
echo x - s-05-2-0-0006a.vhdl
sed 's/^X//' >s-05-2-0-0006a.vhdl <<'*-*-END-of-s-05-2-0-0006a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-0006A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in a configuration body the binding indication may be omitted
X-- from a configuration specification which defines a component instance if
X-- there is neither a select directive which applies to the corresponding
X-- next level configuration nor a configuration specification for the given
X-- component instance in the corresponding architecture body.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity ETY is
Xend ETY;
X
Xarchitecture ABC of ETY is
Xbegin
X BB : block
X component LOCAL
X end component ;
X begin
X CIS : LOCAL;
X end block BB;
Xend ABC;
X
Xconfiguration ONE of ETY is
Xfor ABC
X for BB
X for CIS : LOCAL
X -- NOT-AN-ERROR: Missing Binding Indication is OK.
X-- alias A : integer is B; -- but alias is not..
X end for;
X end for;
Xend for ;
Xend ONE;
X
*-*-END-of-s-05-2-0-0006a.vhdl-*-*
echo x - s-05-2-1-1001a.vhdl
sed 's/^X//' >s-05-2-1-1001a.vhdl <<'*-*-END-of-s-05-2-1-1001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-1402A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that the body indication of a body aspect may be the keyword "OPEN".
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity AZ is
Xend AZ;
X
Xentity ALU is
Xend ALU ;
X
Xarchitecture CYC of ALU is
Xbegin
X BD : block
X signal S1 : Boolean ;
X component B1
X end component;
X begin
X L1 : B1;
X end block BD ;
Xend CYC ;
X
Xarchitecture LYL of ALU is
Xbegin
X CD : block
X component C1
X end component;
X for L2 : C1 use
X entity AZ -- (open)
X-- end for;
X ;
X for L3 : C1 use
X entity AZ -- (open)
X-- end for;
X ;
X begin
X L2 : C1;
X L3 : C1;
X end block CD ;
Xend LYL ;
*-*-END-of-s-05-2-1-1001a.vhdl-*-*
echo x - s-05-2-1-1004a.vhdl
sed 's/^X//' >s-05-2-1-1004a.vhdl <<'*-*-END-of-s-05-2-1-1004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-1401A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that if identification of the design entity is not deferred then the
X-- body aspect may imply any body of the specified kind which is associated
X-- with the implied design entity.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
Xend E;
X
Xarchitecture A of E is
Xbegin
X AB : block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xarchitecture AA of E is
Xbegin
X AB : block
X begin
X process begin null; end process;
X end block;
Xend;
X
Xentity ALU is
Xend ALU ;
X
Xarchitecture CYC of ALU is
Xbegin
X BD : block
X component B1
X end component;
X begin
X L1 : B1;
X end block BD ;
Xend CYC ;
X
Xarchitecture LYL of ALU is
Xbegin
X CD : block
X component C2
X end component;
X begin
X L2 : C2;
X end block CD ;
Xend LYL ;
X
Xconfiguration ONETRY of ALU is
Xfor CYC
X for BD
X for all : B1
X use
X entity E ( A ) ;
X end for ;
X end for;
Xend for ;
Xend ONETRY ;
X
Xconfiguration SECONDTRY of ALU is
Xfor LYL
X for CD
X for all : C2
X use
X entity E ( AA ) ;
X end for ;
X end for;
Xend for ;
Xend SECONDTRY ;
X
*-*-END-of-s-05-2-1-1004a.vhdl-*-*
echo x - s-05-2-1-2001a.vhdl
sed 's/^X//' >s-05-2-1-2001a.vhdl <<'*-*-END-of-s-05-2-1-2001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-05-1-2-1201A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in map aspect association lists any actual designator may be
X-- associated with more than one formal designator.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E1 is
X generic ( iNOA : Integer;
X iNOB : Integer ) ;
X port ( iA : in Bit ;
X iB : in Bit ;
X iCIN : inout Bit ) ;
X
Xend E1;
X
Xarchitecture A1 of E1 is
Xbegin
X A1_BLK : block
X signal S : INTEGER;
X begin
X S <= 1;
X end block;
Xend A1;
X
Xentity EMT is
X generic ( NOA , NOB : Integer ) ;
X port ( A, B : in Bit ;
X CIN : inout Bit ) ;
X
Xend EMT ;
X
Xarchitecture ABC of EMT is
Xbegin
X BB : block
X signal S1 : Integer ;
X component LA
X generic ( SNOA : Integer );
X port( L2A : in Bit ;
X LCIN : inout Bit ) ;
X end component;
X
X for LL : LA
X use
X entity E1 ( A1 )
X generic map ( iNOA => SNOA, iNOB => SNOA )
X port map ( iA => L2A , iB => L2A, iCIN => LCIN )
X ;
X-- end for;
X begin
X LL : LA
X generic map (SNOA => NOA)
X port map (L2a =>A, LCIN => CIN);
X end block BB;
Xend ABC ;
*-*-END-of-s-05-2-1-2001a.vhdl-*-*
echo x - s-05-2-1-2001b.vhdl
sed 's/^X//' >s-05-2-1-2001b.vhdl <<'*-*-END-of-s-05-2-1-2001b.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X --
X -- Copyright Intermetrics 1986
X --
X -- This material may be reproduced by or for the
X -- U.S. Government pursuant to the copyright license
X -- under DAR clause 7-104.9(a) (1981 May)
X --
X --
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: E-05-1-2-1201A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid: -- %G% %W% --
X-- Description:
X-- Check that in port map aspect and generic map aspect association lists
X-- postional association elements are not permitted.
X--
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity EMT is
X generic ( NOA,NOB : integer) ;
X port (A,B : in BIT ;
X CIN : in BIT ;
X Sum : inout BIT;
X COUT : out BIT) ;
Xend EMT ;
X
Xentity Ew is
Xend Ew;
X
X
Xarchitecture ABC of EW is
Xbegin
X BB : block
X signal S1 : integer ;
X component LA
X generic (SOA, SOB : integer);
X port (SA,SB : in BIT;
X SIN : in BIT;
X SSUM : inout BIT;
X SCOUT : out BIT);
X end component ;
X for all : la
X use
X entity EMT
X generic map (SOA,SOB)
X -- Association by position is allowed
X port map ( SA, SB, SIN, SSUM,SCOUT)
X -- Association by position is allowed
X-- architecture(open);
X ;
X-- end for;
X begin
X S1 <= 4;
X end block BB;
Xend ABC;
*-*-END-of-s-05-2-1-2001b.vhdl-*-*
exit
--
Steve Grout @ MCC VLSI CAD Program, Austin TX. [512] 343-0860
ARPA: grout@mcc.arpa
UUCP: {ihnp4,seismo,harvard,gatech,pyramid}!ut-sally!im4u!milano!grout