burke@fps.com (Gary Burke) (01/04/91)
Does any one have non-proprietry yield data on 1-micron CMOS process, or know where I can get this? Gary R Burke.
mark@mips.COM (Mark G. Johnson) (01/04/91)
In article <14477@celit.fps.com> burke@fps.com (Gary Burke) writes: > > Does any one have non-proprietry yield data on 1-micron CMOS >process, or know where I can get this? It perhaps bears repeating that *Yield is a function of time, geographic location, diesize, & die complexity* *Yield is a function of time, geographic location, diesize, & die complexity* *Yield is a function of time, geographic location, diesize, & die complexity* In any given fab, yield on "1-micron CMOS" is better today than it was four years ago; yield increases with time. Similarly, different fabs have different yields even at the same moment of time; building "1-micron CMOS", AMD gets different yield than Cypress and both are different than Motorola, because the fabs are several hundred meters apart in Austin, Texas (USA). Bigger die have lower yields (when yield is expressed as a percentage), because there is more to go wrong with a bigger die. The exact statistical formulae for predicting yield vs. die area are topics of ongoing research and fierce debate; the best treatments (IMHO) are to be found in the IEEE Transactions on Semiconductor Manufacturing. A very broad-brush generalization would be to say that, APPROXIMATELY, Yield = exp(-DA)/f(A) where 0 < Yield < 1 is the fraction of die that are 100% good, A is the die area, D is a positive constant, and f(A) is a function of area. For the widely used "Poisson" yield model, f(A)==1 and thus Yield=exp(-DA). Die complexity enters into the picture because die area doesn't tell the whole story: some chips are pad-limited and have lots of blank-area where there aren't any transistors or wires to fail, other chips like memories are full to the brim with tightly packed dense circuitry and wiring. A first approximation to yield would be a function of 4 variables Yield ~=~ f(t, fab, diearea, complexity). This would be extremely difficult data to find. However, coming up in February, a paper will be given at a conference that might prove helpful. It talks about the yield that a fab must achieve to compete in DRAMs. Given that lots of fabs apparently _do_ manage to compete in DRAMs, the paper probably can be "read backwards" to determine what (a lower bound of) the yield must be. The paper is number 6.1 of the upcoming International Solid State Circuits Conference to be held Feb. 13-15 in San Francisco. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}