[comp.lsi] IEEE Computer Society 1990 VLSI Workshop

paul@odin.m2c.org (Paul Cohen) (12/08/89)

		       IEEE  COMPUTER  SOCIETY
		       1990  WORKSHOP  ON  VLSI
		      February  18  -  21,  1990
			   Tampa,  Florida

Purpose:

The purpose of this workshop is to provide a forum for presentation
and discussion of the progress and problems of current interest in
VLSI. Sessions are planned on the following topics: Synthesis and
Verification, Cad Frameworks, Design for Testability, Interactive
Manufacturing, Design with Programmable Technologies, and Asynchronous
Design For Digital Systems.  Two keynote talks are also scheduled.
    
This annual workshop is sponsored by the IEEEComputer Society
Technical Committee on VLSI and the University of South Florida.

Participation:

All presentations will be given by speakers that the Program Committee
has invited. There will be no proceedings so that the speakers will be
able to present their most recent results and ideas.  Attendance at
the workshop is limited to 80 persons to encourage interaction.

Workshop  Registration:

The registration fee of $200 for IEEE members and $250 for non-members
includes three dinners, three Continental breakfasts, coffee breaks
and workshop fees. The registration form at the end of this mesagage
must be received no later than January 18, 1990.



		       IEEE  COMPUTER  SOCIETY
		       1990  WORKSHOP  ON  VLSI
			   ADVANCE  PROGRAM

Sunday  evening,  February  18


5:30 p.m.  - 6:30 p.m. Registration

6:30 p.m.  - 8:00 p.m. Dinner

8:00 p.m.  - 9:00 p.m. Keynote Session I
                       Session Chairperson
                         Don Bouldin (University of Tennessee)

                       Wafer Scale Integration
                         Earl Swartzlander (TRW)


Monday  morning,  February  19


 8:00 a.m. -  8:30 a.m. Complimentary Breakfast

 8:30 a.m. - 12:00 p.m. Design with Programmable Technologies
                        Session Chairperson
                          Glenn Gulak (University of Toronto)

 8:30 a.m. -  9:15 a.m. Asymptotic Component Densities in Programmable
                        Gate Arrays Realizing All Circuits of a Given Size
                          T. Berger (Cornell University)
                          A. Hekstra (Cornell University)
                          A. Orlitsky (AT&T Bell Laboratories)

 9:15 a.m. - 10:00 a.m.  Architecture and CAD for Digital Field Programmable
                         Gate Arrays
                          Jonathan Rose (University of Toronto)

10:00 p.m. - 10:30 a.m. Break (Coffee/Soft Drinks)

10:30 a.m. - 11:15 a.m. CMOS Field Programmable Analog Arrays
                           K. Lee (University of Toronto)
                           Glenn Gulak (University of Toronto)

11:15 a.m. - 12:00 p.m. Title not available at press time.


Monday  afternoon,  February  19

12:00 p.m. -  2:00 p.m. Lunch on your own

 2:00 p.m. -  5:30 p.m. Asynchronous Design for Digital Systems
                        Session Chairperson
                          Theresa Meng (Stanford University)

 2:00 p.m. -  2:45 p.m. Designing VLSI circuits using Synchronized Transistions
                          Jorgen Staunstrup (Tech.  Univ.  of Denmark)

 2:45 p.m. -  3:30 p.m. Asynchronous Circuits for Signal Processing
                          Robert Brodersen (University of California, Berkeley)

 3:30 p.m. -  4:00 p.m. Break (Coffee/Soft Drinks)

 4:00 p.m. -  4:45 p.m. The Design of the First Asynchronous Microprocessor
                          Alain Martin (CalTech)

 4:45 p.m. -  5:30 p.m. Synthesis of Interface Logic
                          Gaetano Borriello (University of Washington)

 5:30 p.m. -  6:30 p.m. Break


Monday  evening,  February  19

 6:30 p.m. -  7:30 p.m. Dinner


 7:30 p.m. - 8:30 p.m. Keynote Session II
                       Session Chairperson
                         Paul Cohen (Massachusetts Microelecronics Center)

                       VLSI-Based System Design Challenges
                       in the Early 1990's
                          A. Richard Newton (Univ. of California, Berkeley)

 8:30 p.m. - 10:00 p.m. CAD Frameworks
                        Session Chairperson
                          Rick Spickelmier (Univ. of California, Berkeley)

 8:30 p.m. -  9:15 p.m. The CAD Framework Initiative
                          Paul Painter (MCC)

 9:15 p.m. - 10:00 p.m. CAD Frameworks: A Industrial Perspective
                          Tim Barnes (CADENCE)

10:00 a.m. - 10:30 a.m. Break (Coffee)


Tuesday  morning,  February  20

 8:00 a.m. -  8:30 a.m. Complimentary Breakfast


 8:30 a.m. - 12:00 p.m. Design for Testability
                        Session Chairperson
                           Kenneth Rose (Rensselaer Polytechnic Institute)

 8:30 a.m. -  9:00 a.m. BIST Design Methodology Experiment.
                          Sam Duncan (Digital Equipment Corp.)

 9:00 a.m. -  9:30 a.m. Title not available atpress time.
                          Shiang-Ling Wu (AT&T Bell Labs)


 9:30 a.m. - 10:00 a.m. Title not available at press time.
                           Ken Wagner (IBM)


10:00 a.m. - 10:30 a.m. Title not available at press time.

10:30 a.m. - 11:00 a.m. Break (Coffee)

11:00 a.m. - 12:00 p.m. Design For Testability Panel
                        Session Chairperson
                          Kenneth Rose (RPI)

                        Panelists
                          Sam Duncan (DEC)
                          Shiang-Ling Wu (AT&T)
                          Ken Wanger (IBM)


Tuesday  afternoon,  February  20


12:00 p.m. -  2:00 p.m. Lunch on your own


 2:00 p.m. -  5:30 p.m. Synthesis and Verification
                        Session Chairperson
                           Len Berman (IBM)

 2:00 p.m. -  2:45 p.m. Sequential Machine Verification
                          Jean Christohe Madre (Honeywell BULL)

 2:45 p.m. -  3:30 p.m. System Level Verification
                          Dan Beece (IBM Research)

 3:30 p.m. -  4:00 p.m. Break (Coffee/Soft Drinks)

 4:00 p.m. -  4:45 p.m. A Multiple Level Logic Synthesis System Alternating
                        Boolean-Level Adjustment with Gate-Level Evaluation
                          Kazumee Shima (Hitachi)

 4:45 p.m. -  5:30 p.m. Verification of Sequential Machines
                           Carl Seger (Carnegie Mellon University)


 5:30 p.m. -  6:30 p.m. Break 


Tuesday  evening,  February  21


 6:30 p.m. -  8:00 p.m. Dinner


 8:00 p.m. -  9:00 p.m. Panel Session
                        Session Chairperson
                          Len Berman (IBM)

                        System Level Verification - can we make it formal?


Wednesday  morning,  February  21


 8:00 a.m. -  8:30 a.m. Complimentary Breakfast


 8:30 a.m. - 12:00 p.m. Interactive Manufacturing Techniques
                        Session Chairperson
                          Matt Rhodes (Pacific Communication Sciences)

 8:30 a.m. -  9:15 a.m. Highly Conductive Interconnection Laser-Direct-Writing
                       Technology for LSI Restructuring
                         Shunji Kishida (NEC)
                         Yukio Morishige (NEC)

 9:15 a.m. - 10:00 a.m. Title not available at press time

10:00 a.m. - 10:30 a.m. Break (Coffee)

10:30 a.m. - 11:15 a.m. Title not available at press time

11:15 a.m. - 12:00 p.m. Title not available at press time



Hotel  Reservation


The workshop will be held at the Hyatt Regency Westshore in Tampa,
Florida.  A shuttle is available from the Tampa International Airport.
To reserve a room at the conference rate of $100 per night, contact
the hotel directly or the Hyatt toll-free reservation number no later
than January 18, 1990.


                     Hyatt Regency Westshore Hotel
                     6200 Courtney Campbell Causeway
                     Tampa, FL 33607
                     (813)-874-1234
                     (800)-228-9000



Organizing  Committee


D. Bouldin (Univ.  of Tennessee, Knoxville, TN), General Chair
P. Cohen (Mass. Microelectronics Center, Westborough.  MA), Workshop Chair
S. Al-Arian (Univ.  of South Florida, Tampa, FL), Local Arrangements Chair
A. Mukherjee (Univ.  of CentralFlorida, Orlando, FL)
C.K. Wong (International Business Machines, Yorktown Heights, NY)

Technical  Program  Committee

S. Al-Arian (Univ.  of South Florida)
L. Berman (International Business Machines)
D. Bouldin (University of Tennessee)
P. Cohen (Massachusetts Microelectronics Center)
G. Gulak (University of Toronto)
T. Meng (Stanford University)
M. Rho des (Pacific Communication Sciences)
K. Rose (Renssalaer Polytechnic Institute)
R. Spickelmier (University of California, Berkeley)
T. Yanagawa (NEC, Kawasaki, Japan)



For further information and a registration form, contact:

 Don Bouldin (General Chair)
 Department of Electrical Engineering
 420 Ferris Hall
 The University of Tennessee
 Knoxville, Tennessee, 37996-2100
 (615) 974-5444
 bouldin@sun1.engr.utk.edu

 Paul B. Cohen (Program Chair)
 Massachusetts Microelectronics Center
 75 North Drive
 Westborough, MA 01581
 (508) 870-0312
 cohen@m2c.org

 Sami A. Al-Arian (Local Arrangements Chair)
 Computer Science & Engineering Department
 University of South Florida
 Tampa, FL 33620
 (813)-974-3544/4232
 alarian@usf.edu