[comp.lsi] Register file design

marc@CS.UCLA.EDU (05/18/87)

	I am currently designing the datapath of a processor. We
	are implementing some fault-tolerance techniques in the
	design, more specifically around the register file.

	I would like to know if there is any register file design
	available in the following format:
		"MOSIS Scalable CMOS technology"
	
	I am looking for layouts of the following cells:
		- basic register cell (preferably STATIC)
		- register address decoder
		- precharge circuitry
		- sense amplifier

	Thank you for your help,
					Marc Tremblay
					marc@CS.UCLA.EDU