[comp.lsi] Single Error Detection

marc@oahu.cs.ucla.edu (08/25/88)

	I am looking for an "economical" way to implement a Single 
	Error Correction and Double Error Detection (SEC-DED) algorithm.

	So far I am using the following mechanism:

		- 32-bit words along with their 7 encoded Hamming bits 
	   	  are stored in memory.
		- to detect an error upon a "read", a syndrome is
		  generated using 7 XOR gates (~18 inputs). 
		- in case of a fault, the syndrome indicates the 
		  location of the faulty bit. 
		- then the address of the fault is decoded using
		  a *big* decoder.
		- the faulty bit is flipped using a controlled
		  inverter (2-input XOR gate controlled by the
		  decoded line).

	To make things clearer:


		  Data bus and syndrome bits

		  1	2		39
		  |	|	...	|
		  V	V		V
		(----------XOR------------)--> S1
		(----------XOR------------)--> S2
		(----------XOR------------)--> S3
		(----------XOR------------)--> S4	Syndrome bits
		(----------XOR------------)--> S5
		(----------XOR------------)--> S6
		(----------XOR------------)--> S7
		  |	|	...	|      |
		  V	V		V      |
		--------------------------     |
		|      decoder		 |<-----	6 lines go through
		--------------------------		   the decoder
		  |	|	...  |
		  V	V	     V
		 CI    CI	     CI			(Control Inverters)
		  |	|	...  |
		  V	V	     V
		  1	2            32

		      correct word
	    
	    To make things worst we really have two data buses coming
	    together with their 7 check bits, which doubles the logic.
	    First of all the 7 18-input XOR gates take quite a bit of 
	    space then the decoder in its simplest form needs 12 
	    horizontal lines (*2)!

	    Any clever way to reduce the area?

					Marc Tremblay
					marc@CS.UCLA.EDU
					...!(ihnp4,ucbvax)!ucla-cs!marc
					Computer Science Department, UCLA