garyo@masscomp.UUCP (Gary Oberbrunner) (05/16/87)
Here at Masscomp, we are in the final throes of trying to pick an ASIC vendor
who will be able to meet our needs for the next three years. We plan to do
at least 3 to 5 chips per year, most of them fairly ambitious new designs of
over 10,000 gates.
We have managed (mostly) to narrow our decision to VLSI Technology (VTI)
and Silicon Compilers Inc (SCI).
After going over all the technical and business materials and vendor-supplied
references, we find there are still several open issues that we can't
answer. So we decided to post these questions in the hopes that some of
you have completed designs with either of these two vendors and can take a
few minutes to answer the following 18 questions.
The criteria for answering this survey are:
(1) You have completed designs with SCI or VTC and have chips in production.
(2) You have ten minutes to spare. ==== ===== == ==========
Thank you very much for responding - your references will be kept in strictest
confidence, and will be extremely helpful to us in our decision.
Anyone who wants to see the final breakdown should include a return address
and a not to that effect in her/his mail. Oh yeah - please respond ONLY
by mail directly to me - ...{harvard,allegra}!masscomp!garyo.
Thanks again.
- Gary Oberbrunner MASSCOMP
...{harvard,allegra,ihnp4}!masscomp!garyo 1 Technology Park
Westford, MA 01886
(617) 862-8836 x2445
--------------------------MASSCOMP ASIC VENDOR SURVEY -----------------------
0. Who are you? What did you design, with whom, and when?
1. Was the first pass of the device used in production?
2. Have you respun the device subsequently? Why?
3. Was there PCB compensation for problems with the device?
4. Did the performance of the part meet your expectations for the
silicon technology used?
5. How did the performance of the part match the numbers predicted by
the timing verifier?
6. Which silicon process was used? When was the design done relative
to the availability of the process and tools?
7. With what version of the tools was the project done?
8. Were there problems with the tools that required work-arounds?
9. What features of the system were used? Specifically, what
features were found to be particularly useful?
10. What features of the system were not used? Specifically, what
features were found to not be useful or were not working?
11. Did the tools change while doing the design? If so, did the tool
change have any impact on the design?
12. Did the device characterization change during the design? If so,
how?
13. How much of the design was asynchronous?
14. How long did it take to simulate? Specifically, how long did the
process of simulation/debug take in calendar time as well as
how long did the actual simulation runs take. What was the
simulator performance?
15. What was the simulation methodology? Diagnostic style? How was
the stimulus generated? How were results checked? How were
production test vectors generated?
16. Were tools other than those supplied by the vendor used? Which
and why? Was a physical breadboard made of the design? Was it a
compaction of an existing design or was it a design from scratch?
16. Was the design modified to improve performance? Were compiled
blocks redesigned at a lower logic level to improve performance?
How late in the process was the performance of the device
determined?
17. Was the design done in house or at a design center? What was the
level of support received?
18. If you were to do another design, would you choose the same
vendor?
--
Remember, -Truth is not beauty;
Information is not knowledge; / Beauty is not love; Gary Oberbrunner
Knowledge is not wisdom; / Love is not music; ...!masscomp!garyo
Wisdom is not truth; ----/ Music is the best. - FZ