[..] comp.lsi.cad

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Looking for Magic (0 replies, 06/24/88)

more CAD tool notes (0 replies, 06/28/88)

VHDL simulator wanted (0 replies, 07/08/88)

A New Switch Level Simulator (1 reply, 07/15/88)

Magic driver for X-11 available from expo (0 replies, 07/20/88)

Current version of Spice? (1 reply, 07/22/88)

RNL (0 replies, 07/29/88)

Where to start in lsi (1 reply, 08/24/88)

Fast parts from CAD tools? (0 replies, 08/25/88)

DRC for KIC (2 replies, 08/25/88)

MEXTRA (1 reply, 08/26/88)

Spice runtime vs # of transistors (1 reply, 08/30/88)

What to do with AED512 (0 replies, 09/01/88)

Automatic layout (0 replies, 09/02/88)

CMOS3 cells in Oct (0 replies, 09/07/88)

CIF to Postscript program to be posted (0 replies, 09/09/88)

cif to PostScript (3 replies, 09/09/88)

Has anyone used Phase 3 schematics capture software on Suns? (0 replies, 09/11/88)

Info on Logic Synthesis Packages needed (0 replies, 09/19/88)

timing verification (0 replies, 10/15/88)

Source Code For a New Switch Level Simulator (0 replies, 11/06/88)

Switch Level Integrated Circuits (3 replies, 11/11/88)

Help needed: magtape format for Patterngenerator (0 replies, 11/23/88)

SLIC Improved (0 replies, 11/24/88)

SLIC Update (0 replies, 11/24/88)

SLIC Updated Source Code (0 replies, 11/24/88)

enhancement to magic/ext2sim/sim2spice (0 replies, 11/30/88)

CAD for ASIC's, PLD's, PAL's and PCB's (2 replies, 12/04/88)

Who is using VIEWLOGIC software? (0 replies, 12/06/88)

SPICE3B1 sunview interface (0 replies, 12/09/88)

FutureDesigner and DASH-ABEL (1 reply, 12/13/88)

Spice3b1 - URC problem (0 replies, 12/13/88)

MOSIS compatible technology files for GDT. (0 replies, 12/19/88)

Need Help from MAGIC Users (0 replies, 12/29/88)

Need Help from MAGIC or PSPICE Users (0 replies, 12/30/88)

high-density hybrid designs (0 replies, 01/06/89)

Magic modifications wanted (0 replies, 01/13/89)

Help: Would you share your experience on schematic capture tools? (0 replies, 01/26/89)

Testability Analysis Tools (0 replies, 01/30/89)

CAD tools (1 reply, 02/01/89)

CAD Framework Initiative Meeting on FEB 16-17 and CFI info (0 replies, 02/02/89)

Help hooking Versatec plotter to Suns (0 replies, 02/04/89)

EDIF databases? (1 reply, 02/07/89)

Intermediate format transaltors (0 replies, 02/07/89)

Mextra, cif utils on Sun IV 4.0.1 (0 replies, 02/16/89)

Mentor Graphics software (2 replies, 02/18/89)

Synthesis and Testing (0 replies, 02/19/89)

CIF -> HPGL (1 reply, 02/19/89)

MAGIC on MicroVAX (1 reply, 02/21/89)

Magic on 386 Machines? (0 replies, 02/22/89)

"CIFP" Package for HP 7570A Plotter (0 replies, 02/24/89)

VAMP McCAD EDS-1 Software (0 replies, 03/09/89)

EMI Analysis Programs (0 replies, 03/10/89)

Call for discussion - Proposed VHDL News Group (0 replies, 03/13/89)

Autocad (0 replies, 03/22/89)

PROTOTYPE CHIPS, MULTI-PROJECT CHIPS - NEED INFO (2 replies, 03/23/89)

CAD Benchmarks available (0 replies, 03/23/89)

MFBCAP for SUN ? (0 replies, 03/25/89)

Magic tech file for floating gates ... (0 replies, 03/31/89)

cif2egs program (0 replies, 03/31/89)

plot (0 replies, 03/31/89)

Wired-OR in VLSI (0 replies, 04/01/89)

KIC2 to X-Windows: anyone done it? (0 replies, 04/01/89)

Sim2scope and caesar in Sun 3/60 (0 replies, 04/05/89)

Spice2g6 Memory Limit Problem (0 replies, 04/06/89)

desperately seeking polygon help (0 replies, 04/06/89)

CAD packages (0 replies, 04/06/89)

C-Spice (0 replies, 04/07/89)

AI applied to VLSI Design (0 replies, 04/08/89)

Seeking Gate-level simulator (0 replies, 04/09/89)

WORKSHOP LOGIC SYNTHESIS MAY 23-26, 1989 (0 replies, 04/12/89)

Faster than SPICE (2 replies, 04/12/89)

X terminals of workstations (1 reply, 04/14/89)

Parallel Simulated Annealing / References and Are You Doing It? (0 replies, 04/14/89)

26th DAC (0 replies, 04/16/89)

Announcement (0 replies, 04/16/89)

CAD/CAM systems using commercial databases (2 replies, 04/19/89)

Latest Vivid features? (2 replies, 04/22/89)

Gate Simulator Followup (0 replies, 04/27/89)

CIF plot on HP plotters? (2 replies, 04/27/89)

KIC2 question (0 replies, 04/30/89)

Looking for test pattern generation programs (0 replies, 05/01/89)

SIGDA Workshops (0 replies, 05/03/89)

3rd European EDIF Forum (0 replies, 05/03/89)

RNL and RSIM (0 replies, 05/03/89)

SPICE probs (3 replies, 05/03/89)

LSI CAD tool opinions wanted (3 replies, 05/04/89)

Prolog Algorithm (0 replies, 05/04/89)

Ella example designs wanted (0 replies, 05/09/89)

Network Editor wanted (1 reply, 05/10/89)

Need a file from BOLD distribution ... (0 replies, 05/10/89)

X11 xsplot (1 reply, 05/12/89)

Any experience with the DesignWorks electronic CAD system for the Mac? (0 replies, 05/12/89)

Electronic CAD device model questions (0 replies, 05/12/89)

CAD/CAM/CAE newsgroup proposal (9 replies, 05/15/89)

File Format Specifications (0 replies, 05/18/89)

OCT documentation (0 replies, 05/24/89)

VHDL IEEE Std - Reference Manuals (0 replies, 05/24/89)

Spice problems on Ultrix-32 V3.0 (0 replies, 05/26/89)

IEEE Standards activities --> Info on Design Automation Stds (0 replies, 05/27/89)

Oct Tool Set Question.......... (1 reply, 05/30/89)

Looking for room mate at DAC 89 (0 replies, 05/31/89)

A MODIFIED Call for discussion - Proposed VHDL News Group (2 replies, 06/01/89)

Need cifplot for HP plotter (0 replies, 06/02/89)

CMOS3 and CMOS2 cell libraries; CMOS VLSI Design Book (1 reply, 06/06/89)

VHDL Simulator (1 reply, 06/10/89)

Board Layout editor wanted (0 replies, 06/22/89)

Greenfield (1 reply, 06/24/89)

Layout Editor wanted ! (3 replies, 06/27/89)

Latest version of MAGIC (2 replies, 06/29/89)

Unix VLSI CAD Systems an Tools (0 replies, 07/06/89)

Unix VLSI CAD Systems and Tools (0 replies, 07/06/89)

X11 and Magic (0 replies, 07/07/89)

schematic verification tool (0 replies, 07/08/89)

GDSII read/write routines (0 replies, 07/18/89)

Valid (0 replies, 07/18/89)

VHDL - IEEE Standard (2 replies, 07/27/89)

Electric on the Macintoy (0 replies, 07/28/89)

Need layout program for test devices (0 replies, 07/28/89)

Need to find latest version of ELECTRIC (0 replies, 07/29/89)

Request for info on 'Espresso' (0 replies, 08/02/89)

Third European EDIF Forum (0 replies, 08/03/89)

Spice Level 3 charge modeling (0 replies, 08/04/89)

Magic source (1 reply, 08/04/89)

SunOS-4.0.3 breaks Magic (0 replies, 08/08/89)

Magic portability (0 replies, 08/08/89)

Magic on SunOS-4.0.3 (0 replies, 08/09/89)

Junior/Senior Positions in CAE/Logic Simulation Available in Silicon Valley (0 replies, 08/13/89)

EDIF NETLIST examples (0 replies, 08/15/89)

non-Manhattan layout tool (1 reply, 08/25/89)

Simulators ? (0 replies, 08/26/89)

EDIF World is Near (0 replies, 08/30/89)

new MOSIS' SCMOS.TECH for Magic4.10 ..... (0 replies, 08/30/89)

Simulation for analog VLSI (0 replies, 08/30/89)

Power estimation of ECL circuits (0 replies, 09/05/89)

X interface to spice3b1 (0 replies, 09/06/89)

Power and ground routing. (0 replies, 09/06/89)

OCT (0 replies, 09/07/89)

ECL GATE ARRAY ROUTERS - ANY EXPERIENCE/RECOMMENDATIONS? (0 replies, 09/07/89)

MPLA on a Sun 4... (0 replies, 09/07/89)

VHDL compiler/simulator (0 replies, 09/08/89)

cifplot for HP 7221 (0 replies, 09/12/89)

Cifplot for Postscript Printers? (0 replies, 09/12/89)

Looking for KIC2 sources running under X11 (0 replies, 09/13/89)

Cifplot for Postscript Printers (0 replies, 09/13/89)

Hardware Verifiers Available (0 replies, 09/14/89)

Analog vlsi simulation: Summary (0 replies, 09/16/89)

Spice, bsim level of simulation (0 replies, 09/16/89)

BSIM model in SPICE (0 replies, 09/16/89)

Syntax error in X10.h (0 replies, 09/16/89)

EDIF Draft Standard Available? (0 replies, 09/17/89)

MPLA patch request (0 replies, 09/17/89)

FABRICS II user guide (0 replies, 09/17/89)

Magic Version 6 BETA test sites wanted (0 replies, 09/19/89)

Berkeley tools (1 reply, 09/21/89)

Benchmark Digital Circuits for testing Simulator (0 replies, 09/21/89)

Help Selecting System (0 replies, 09/22/89)

DynaCaDD for the Atari ST forsale (0 replies, 09/25/89)

How to get Boyer-Moore Theorem Prover (0 replies, 09/27/89)

Help on HP 7221C Plotter (0 replies, 09/27/89)

Magic and color postscript... (0 replies, 09/28/89)

PC Tools for Boolean Equations (2 replies, 09/30/89)

octtools or Menter Graphics' package (2 replies, 10/01/89)

DAC Call for Papers Deadline Approaching (0 replies, 10/03/89)

Electric & Magic (0 replies, 10/03/89)

3rd European EDIF Forum -- Preliminary Programme 12,13 October 1989 (0 replies, 10/03/89)

Request for circuits in Neutral Netlist of 10 Combinational Benchmark.. (1 reply, 10/04/89)

Plotting Packages (0 replies, 10/05/89)

supercrystal (0 replies, 10/07/89)

magic extraction (2 replies, 10/17/89)

Steiner tree implementation (0 replies, 10/17/89)

Software Needed Urgently! (0 replies, 10/19/89)

Don't cares accepted by OCT/misII? (0 replies, 10/20/89)

Need pointer to CIF2HPGL (0 replies, 10/25/89)

VHDL test examples (3 replies, 10/25/89)

Double Layer Metal CMOS Circuit Layouts Required. (0 replies, 10/26/89)

Recommendations for university EECE program requested (0 replies, 10/27/89)

Automatic transistors sizing (1 reply, 10/27/89)

DAC Call For papers deadline is one week away (0 replies, 10/31/89)

newsgroup content (1 reply, 10/31/89)

Where do I get Magic, etc. for Sun4 (5 replies, 10/31/89)

SPICE parameter averaging? (0 replies, 11/09/89)

OCT Problem (2 replies, 11/11/89)

request info - magic on 3100? (0 replies, 11/13/89)

PD EDIF v200 syntax checker for IBM PC (0 replies, 11/16/89)

Cadence Users Group Software Exchange (0 replies, 11/17/89)

ICCAD 89 Proceedings (0 replies, 11/17/89)

Floorplanning Package (0 replies, 11/20/89)

Skill (0 replies, 11/20/89)

plotting (0 replies, 11/21/89)

Tanner Research Tools (0 replies, 11/21/89)

seeking linear analog ckts (0 replies, 11/21/89)

Need help on Silos input commands ... (3 replies, 11/22/89)

edif icon for suntools (0 replies, 11/23/89)

Talk us out of using SPICE (0 replies, 11/27/89)

How many Analog design tools are "public domain"? (0 replies, 11/28/89)

parasitic circuit extraction from EDIF (0 replies, 11/28/89)

Versatec RPM memory upgrade?? (0 replies, 12/02/89)

Summer School on Formal Methods for VLSI Design (0 replies, 12/04/89)

Research Assistant job (0 replies, 12/05/89)

IEEE Computer Society 1990 VLSI Workshop (0 replies, 12/08/89)

ISSCC errata (1 reply, 12/14/89)

Single_output option of ESPRESSO (0 replies, 12/19/89)

Looking for newer versions of Crystal (0 replies, 12/19/89)

test sites needed ... (1 reply, 12/20/89)

description language MODEL (1 reply, 12/21/89)

Gate Array Design Program for IBM PC-AT (0 replies, 01/04/90)

Computer Engineering/Computer Science Monograph (0 replies, 01/05/90)

Artificial Intelligence Editor Wanted (0 replies, 01/05/90)

Journal/Progress Series authors wanted (0 replies, 01/05/90)

Articles on UDL/I (0 replies, 01/07/90)

MOSIS' net-list-to-parts test sites... (0 replies, 01/11/90)

Research assistant (0 replies, 01/13/90)

conference proceedings (0 replies, 01/17/90)

Calma Extraction Tools? (2 replies, 01/17/90)

looking for ideas (1 reply, 01/18/90)

VHDL information (0 replies, 01/19/90)

simulation techniques info requested (0 replies, 02/06/90)

GDSII to CIF (0 replies, 02/13/90)

BiCMOS (0 replies, 02/13/90)

Request for Description of ORCAD .SCH binary format (0 replies, 02/14/90)

Request for info on Parallel Discrete Event Simulation (0 replies, 02/19/90)

Gerber display utilities? (0 replies, 02/21/90)

WANTED: Cif Plotting Tool for CalComp plotters (0 replies, 02/22/90)

Tiling Custom Cells Using the OCT Tools (0 replies, 02/22/90)

design styles for MPLA (0 replies, 02/22/90)

Looking for information about WAVES/VHDL (0 replies, 02/23/90)

Surplus Calma GDSII dealers? (0 replies, 02/23/90)

bugfixes to magic 4.10 under X.V11R[34]/Decwindows wanted (0 replies, 02/23/90)

Two positions (0 replies, 02/24/90)

finite el. anal. code (0 replies, 02/28/90)

Help: is there anyone willing to let me ftp "wombat" from UCB? (0 replies, 02/28/90)

Models for BiCMOS and GaAs (0 replies, 02/28/90)

What does SPICE stand for?? (1 reply, 03/01/90)

Mentor/Cadence (0 replies, 03/02/90)

Workstation Info Wanted (2 replies, 03/02/90)

MAGIC problem (0 replies, 03/06/90)

genesil (0 replies, 03/06/90)

PLA files (0 replies, 03/07/90)

ISCAS '89 test generation benchmark data (3 replies, 03/09/90)

SPICE3C.1 (0 replies, 03/10/90)

OCTTOOLS MISII Synthesis Questions (1 reply, 03/19/90)

Fault grading of VLSI (1 reply, 03/22/90)

OCT tools (0 replies, 03/22/90)

Routing of power/ground nets. (0 replies, 04/14/90)

CFP - EDIF WORLD `90 (0 replies, 04/26/90)

X based Magic? (0 replies, 05/04/90)

Request for refs on object-oriented digital CAD systems (0 replies, 05/24/90)

CAD system wanted (0 replies, 05/25/90)

circuit simulatots (0 replies, 05/26/90)

gerber format (0 replies, 05/30/90)

Summary -- arithmetic operators using octtools (1 reply, 05/30/90)

Microwave CAD (0 replies, 05/31/90)

High Level Synthesis (1 reply, 05/31/90)

Results of X windows CAE/EDA survey. (0 replies, 05/31/90)

VLSI TOOLS (0 replies, 06/02/90)

placement paper (0 replies, 06/04/90)

CALL FOR VOTES -- comp.cad.mech (1 reply, 06/04/90)

standard cell based synthesis (0 replies, 06/04/90)

SEEK REFERENCE FOR INCOMPLETE OR PARTIAL VALUED LOGIC IN VLSI CIRCUITS (0 replies, 06/05/90)

VHDL vs Verilog (0 replies, 06/07/90)

Help needed for Mpanda / Mpack... (0 replies, 06/09/90)

Question about netlist description in EDIF 200 (1 reply, 06/15/90)

genesil at 10.2 (0 replies, 07/04/90)

CLSI VHDL Tool Integration Platform (0 replies, 07/05/90)

Need gate level logic simulator (0 replies, 07/10/90)

VLSI/MicroChip Design Tools (4 replies, 07/12/90)

IPC standards (0 replies, 07/12/90)

Looking for espresso logic reduction program (0 replies, 07/12/90)

Seeking a lisp.h file for Chris Terman's RSIM, etc. (0 replies, 07/14/90)

PLA Benchmarks (1 reply, 07/19/90)

Looking for THOR (0 replies, 07/21/90)

The `Common Simulation Data Format (0 replies, 07/23/90)

"L" language (0 replies, 07/24/90)

Annoucement European EDIF Forum 1990 (0 replies, 07/25/90)

mextra for sun4? (0 replies, 07/28/90)

VHDL- need help (1 reply, 07/28/90)

EDIF World `90 (0 replies, 07/29/90)

[Wanted] Maclogic & MacBridge (0 replies, 07/30/90)

VLSI Design Tools on PCs (5 replies, 07/30/90)

Book on Verilog HDL (4 replies, 08/07/90)

Gate Matrix CAD software (0 replies, 08/08/90)

Help! Expresso PLA file format (1 reply, 08/09/90)

SPICE3 (1 reply, 08/10/90)

questions on EDIF semantics (2 replies, 08/11/90)

no PALASM90 on workstations (16 replies, 08/12/90)

VHDL Standard Logic Package (0 replies, 08/14/90)

CAD tools for Silicon Micromachining (0 replies, 08/14/90)

Looking for X11 Driver for PLOTCAP (0 replies, 08/15/90)

automatic circuit object identification? (0 replies, 08/16/90)

Porting MAGIC to IBM's RS/6000 (0 replies, 08/17/90)

Viewlogic Workview 860 suite (0 replies, 08/20/90)

Any MAGIC wizards out there ? (0 replies, 08/20/90)

V HDL (1 reply, 08/21/90)

Opinion on AutoCAD (0 replies, 08/21/90)

Connection machine (0 replies, 08/21/90)

Software for schematics? (0 replies, 08/21/90)

Synopsys FSM syntax question (0 replies, 08/22/90)

Magic for Sun 4? (0 replies, 08/23/90)

Instructional PC CAD Tools (0 replies, 08/24/90)

VHDL newsgroups and mailing lists (0 replies, 08/24/90)

VHDL public domain models (0 replies, 08/24/90)

X-servers (0 replies, 08/30/90)

Pads in octtools (0 replies, 08/30/90)

CIF and octtools (1 reply, 08/30/90)

Magic on Sun 4/110s ?? (0 replies, 08/31/90)

Desperately Seeking Micromachining CAD Software (0 replies, 08/31/90)

Magic on DOS (0 replies, 08/31/90)

SUMMARY to Any MAGIC wizards out there ? (0 replies, 09/04/90)

HELP - CIF or GDS2 (0 replies, 09/05/90)

bug in magic stream output for arrays (0 replies, 09/06/90)

Magic for IBM RS/6000 (0 replies, 09/07/90)

CALMA systems for sale (0 replies, 09/11/90)

SASIMI'90 (0 replies, 09/12/90)

VHDL mailing list (0 replies, 09/12/90)

How can I place vias over contacts in magic? (0 replies, 09/13/90)

Some info on VHDL (1 reply, 09/13/90)

Orbit/Foresight 1.2um twin well Magic design rules file (0 replies, 09/14/90)

MIS multilevel logic optimization system question (0 replies, 09/14/90)

D-algorithm implementation (0 replies, 09/14/90)

using CAD output for model-based diagnosis (0 replies, 09/17/90)

request info on CAD standards: EDIF, VHDL, IGES (0 replies, 09/17/90)

Request for place-and-route netlist (3 replies, 09/17/90)

Full-Custom VLSI Design -- Employment Wanted. (0 replies, 09/17/90)

Help needed in VHDl (0 replies, 09/18/90)

CIF user extensions (0 replies, 09/20/90)

VLSI Layout (0 replies, 09/20/90)

VLSI Technology place and route tools for gate arrays (5 replies, 09/20/90)

Where can I run STAFAN? (0 replies, 09/22/90)

checking sim files (2 replies, 09/22/90)

integer linear programming -- data (0 replies, 09/24/90)

Copies of Dissertation and Digital Simulator Available (0 replies, 09/25/90)

Fugu: 3D tool for Pisces IIB & Suprem IV (0 replies, 09/26/90)

Fugu: PostScript example (0 replies, 09/26/90)

Info on CAD and/or CAM Systems (0 replies, 09/27/90)

Info wanted on MBR for digital hardware diagnosis (0 replies, 09/27/90)

Magic Version 6 now available (1 reply, 09/28/90)

High-Level Synthesis (2 replies, 09/28/90)

Berkeley VLSI Tools besides Magic? (0 replies, 09/30/90)

Question: EDIF version? (0 replies, 10/01/90)

Info needed on TimberWolf3.2 package (0 replies, 10/02/90)

VHDL question : Need Help (1 reply, 10/02/90)

Channels Wanted (0 replies, 10/06/90)

Opcode assignment for RISC processors (2 replies, 10/07/90)

mextra - circuit extractor for VLSI simulation (0 replies, 10/08/90)

PCB interconnect simulation -- job offered (0 replies, 10/11/90)

PCB Heat transfer Simulation (0 replies, 10/11/90)

Transistor testing in octtools (0 replies, 10/14/90)

CALL FOR DISCUSSION comp.lang.vhdl (0 replies, 10/15/90)

Compiling mpla in magic6 release problems (0 replies, 10/16/90)

BiCMOS through MOSIS (1 reply, 10/17/90)

Graph-based IR (0 replies, 10/18/90)

1991 Advanced Research in VLSI paper deadline extended (0 replies, 10/19/90)

CALL FOR DISCUSSION: comp.lang.vhdl (0 replies, 10/19/90)

Failure modes in large, simple, electrical circuits (0 replies, 10/22/90)

Looking for SPICE doc's (0 replies, 10/24/90)

Cadence VLSI design tool evaluations wanted..... (0 replies, 10/25/90)

Simulation Workshop (0 replies, 10/25/90)

ISP Reference? (1 reply, 10/25/90)

List of logic synthesis systems, help needed (1 reply, 10/25/90)

Magic V6 on magnetic tape (0 replies, 10/26/90)

need info on picture editor (0 replies, 10/26/90)

AutoCAD on HP/APOLLO Series 9000 Model 400 (0 replies, 10/31/90)

plotting from magic 6 (0 replies, 11/01/90)

SPICE3C1, BSIM and no convergence (0 replies, 11/01/90)

Looking for references to a circuit-drawing program (3 replies, 11/03/90)

Summary: Graph-based intermediate representations. (0 replies, 11/04/90)

Pisces IIb... (1 reply, 11/05/90)

Looking for sim2spice which handles double-poly process (0 replies, 11/05/90)

IRSIM and T-gates (0 replies, 11/05/90)

EDIF info needed (0 replies, 11/07/90)

IRSIM parameter file for 1.2um MOSIS SCMOS (0 replies, 11/07/90)

Looking for MAGIC v6.3 GaAs tech file (0 replies, 11/08/90)

looking for chkn (0 replies, 11/08/90)

RS6000 and CAD Tools (0 replies, 11/09/90)

>32 bit integers (0 replies, 11/09/90)

Need to use the Magic database for layer representation (0 replies, 11/09/90)

SCS/Mentor users group? (1 reply, 11/10/90)

Clock Routing (0 replies, 11/10/90)

Looking for X schematic editor (0 replies, 11/11/90)

Error in net-address. (0 replies, 11/11/90)

Fintronic USA got UDL/I development (0 replies, 11/13/90)

Pisces vs Cande (0 replies, 11/13/90)

IRSIM response (0 replies, 11/13/90)

Geometric CAD (0 replies, 11/14/90)

Query on the accuracy of circuit simulators (0 replies, 11/14/90)

An IRSIM prm file for 1.2um (0 replies, 11/14/90)

Levelized Compiled Code Simulators (0 replies, 11/16/90)

PCB Router (0 replies, 11/16/90)

What is the newest version of Crystal? (0 replies, 11/16/90)

How to write a Calma tape? (1 reply, 11/16/90)

GDSII to Gerber conversion wanted (0 replies, 11/16/90)

MINIMOS 5 (0 replies, 11/19/90)

npn tranistors in magic (1 reply, 11/20/90)

CMOS generators for Magic (0 replies, 11/20/90)

CMOS pla generator for Magic (0 replies, 11/20/90)

Faculty Positions (0 replies, 11/21/90)

CALL FOR VOTES: comp.lang.vhdl (1 reply, 11/26/90)

Free Digital Design Software (0 replies, 11/27/90)

MAGIC VLSI FONTS (0 replies, 11/27/90)

Need L to CIF converter (0 replies, 11/30/90)

new newsgroup for the VHDLs, Now: VHDL (0 replies, 11/30/90)

Physical Design Workshop II (0 replies, 12/02/90)

Available Design Tools (2 replies, 12/05/90)

GERBER data format tool (0 replies, 12/05/90)

new newsgroup for the VHDLs (5 replies, 12/06/90)

VHDL Help (0 replies, 12/07/90)

"Inexpensive" EE design tools (0 replies, 12/08/90)

Info on how to get the latest Spice3 (2 replies, 12/09/90)

Circuit simulator benchmarks (7 replies, 12/11/90)

standard graphics/CAD file formats? (0 replies, 12/12/90)

Research Assistantships in Formal Methods in VLSI (0 replies, 12/12/90)

Scaling from 3.0um technology to 1.25um technology (0 replies, 12/13/90)

Available Design Tools -- PLD (1 reply, 12/13/90)

Survey of HDL users (0 replies, 12/13/90)

N.2 availability (0 replies, 12/13/90)

HDLs (0 replies, 12/14/90)

CAzM (1 reply, 12/14/90)

ACE Hardware Description Language (0 replies, 12/14/90)

help reqd. in VHDL (0 replies, 12/15/90)

Re : need help in VHDL (0 replies, 12/15/90)

Viewlogic CAE System (0 replies, 12/18/90)

MAGIC ver 6.3 -----Problems in resistance extraction (0 replies, 12/19/90)

Magic Extraction Bug Fixes (0 replies, 12/19/90)

Looking for a magic port to RS/6000 (0 replies, 12/19/90)

Resistance extraction bug in magic v.6 (2 replies, 12/20/90)

comp.lang.vhdl passes successfully (0 replies, 12/21/90)

Help needed on vectorising the Scanner inputs (0 replies, 12/22/90)

Simulator performance (0 replies, 12/22/90)

Patches to SPICE 3D2 (0 replies, 12/26/90)

Need info for LSI CAD's for a PC (2 replies, 12/26/90)

Magic: How do I get it? (1 reply, 01/02/91)

Cambridge HOL System - 5-day intensive course (0 replies, 01/04/91)

P-CAD driver wanted (0 replies, 01/04/91)

newsgroup for VHDL (0 replies, 01/07/91)

SIS logic optimizer (0 replies, 01/08/91)

1991 IEEE-CS VLSI Workshop (0 replies, 01/08/91)

CADKEY (0 replies, 01/09/91)

MAGIC on the RS/6000 (0 replies, 01/09/91)

looking for newsgroups or mailing lists on VLSI and image processing (0 replies, 01/11/91)

Capacitance extraction with dracula (1 reply, 01/15/91)

Magic 1.25um Scmos Pad Frames & Pads (1 reply, 01/17/91)

need translator to generate magic file from yacr output (0 replies, 01/18/91)

GDSII<->PostScript<->HPGL translation pgms wanted (0 replies, 01/19/91)

Spice questions (0 replies, 01/19/91)

WANTED: Information on Operating System Simulation (0 replies, 01/23/91)

compare SPICE3D2 and HSPICE (0 replies, 01/23/91)

FTP access to SPICE3D2 issues (0 replies, 01/23/91)

Lossy transmission lines / QUAD ? (4 replies, 01/23/91)

Benchmarks for Boundary Scan (0 replies, 01/30/91)

want logic simulation program (0 replies, 01/31/91)

List of synthesis systems (0 replies, 01/31/91)

Porting Magic6.0 onto the RS6000 (0 replies, 02/04/91)

Need info about CFI (0 replies, 02/04/91)

VHDL syntax (0 replies, 02/05/91)

Need info on CFI (0 replies, 02/05/91)

Call for Contributions: Oxford Field Programmable Logic Workshop (0 replies, 02/06/91)

ICCAD-91 Call for Papers (0 replies, 02/06/91)

ISCAS '85 Benchmark Circuits (0 replies, 02/06/91)

Need guidance using Octtools 4.0 to create a dual ported register file (0 replies, 02/07/91)

SPICE parameters for GaAs BJT's or diodes (0 replies, 02/07/91)

CIF->PS VLSI geometry description (0 replies, 02/07/91)

call for papers (0 replies, 02/09/91)

Effective Resistance of MOSFETs (0 replies, 02/10/91)

IRSIM (2 replies, 02/11/91)

Tiff to polyline converter wanted. (0 replies, 02/11/91)

Availability of latest version of SPICE3 (0 replies, 02/12/91)

<None> (1 reply, 02/13/91)

GDT MOSIS process files needed (0 replies, 02/14/91)

Placement-benchmarks (0 replies, 02/15/91)

Muller C-Elements (0 replies, 02/17/91)

Large placement benchmarks needed (0 replies, 02/18/91)

Looking for mpla binary for Sun-SLC (0 replies, 02/20/91)

Magic for DOS (0 replies, 02/21/91)

References on Object Oriented VLSI CAD, please? (0 replies, 02/26/91)

DFT91 - CALL FOR PAPERS (0 replies, 02/26/91)

Bugs in Suprem4 (1 reply, 02/28/91)

GDSII stream format (1 reply, 03/01/91)

problems compiling spice3c1 (0 replies, 03/03/91)

Test Generation Benchmarks (0 replies, 03/05/91)

Lengths data from CIF files (0 replies, 03/06/91)

Full complementary CMOS tiles for mpla? (0 replies, 03/06/91)

Suprem4 & Pisces interface to NCSA (0 replies, 03/08/91)

? Grammar for Dracula ? (0 replies, 03/09/91)

IRSIM and Magic 6.3, tut11a (0 replies, 03/09/91)

Olympus Synthesis (0 replies, 03/09/91)

future bus, transmission line, simulation (2 replies, 03/13/91)

C to Verilog HDL (0 replies, 03/13/91)

Question on ACTOR (0 replies, 03/13/91)

Friendly Interface to MOSSIM available? (0 replies, 03/13/91)

INTO CLASS PROJECTS (0 replies, 03/13/91)

Automatic Test Pattern Generators (0 replies, 03/13/91)

User Friendly MOSSIM Avaliable? (0 replies, 03/13/91)

User Friendly Mossim available? (0 replies, 03/13/91)

"Intelligent" extractors for CIF? (0 replies, 03/14/91)

Explaination of SPICE3C1 Messages Needed (1 reply, 03/14/91)

CIF read into Magic 6.3 (0 replies, 03/14/91)

SPICE simulators info req (0 replies, 03/14/91)

Looking for timing diagram drawing tool (0 replies, 03/15/91)

? Grammar for Cadence Dracula ? (1 reply, 03/15/91)

magic well contact problem (0 replies, 03/19/91)

Berkely Spice (0 replies, 03/19/91)

Modeling of ideal diodes in (1 reply, 03/20/91)

Looking for information (0 replies, 03/20/91)

MPLA, MPACK on Magic 6.3? (0 replies, 03/22/91)

To find new Magic Package (0 replies, 03/22/91)

VLSI EXPERT PLEASE READ (1 reply, 03/22/91)

Needed: mpack from Magic 4 (1 reply, 03/22/91)

5-day Course on Cambridge HOL System (0 replies, 03/23/91)

Verilog --> FPGA Conversion (1 reply, 03/23/91)

verilog query (1 reply, 03/25/91)

Third Physical Design Workshop (0 replies, 03/25/91)

Status of SuperCrystal? (0 replies, 03/27/91)

"Timing Simulation....." (0 replies, 03/27/91)

Modeling inductors in Lsim (0 replies, 03/27/91)

Espresso and MIS (0 replies, 03/28/91)

Formation of the newsgroup Comp.lsi.cat (0 replies, 03/28/91)

Call For Discussion: Comp.lsi.CAT (0 replies, 03/28/91)

Formation of comp.lsi.cad.test (1 reply, 03/29/91)

comp.lsi.cat (1 reply, 03/29/91)

New groups.. (0 replies, 03/29/91)

Computer Aided Test Group (0 replies, 03/30/91)

Minimizing Logic (0 replies, 04/01/91)

Autodesk Animator info. (0 replies, 04/01/91)

Actel FPGA Design Software Question... (0 replies, 04/03/91)

CIF to GDSII conversion (0 replies, 04/03/91)

CIF definition (0 replies, 04/03/91)

CAD Framework Initiative (0 replies, 04/04/91)

AutoCAD Convert 11 to 10 (0 replies, 04/05/91)

edge2.1 symbolic layout and ES2 technology?? (0 replies, 04/08/91)

DOS background tasker for AutoCAD. (0 replies, 04/10/91)

Need help on supercrystal for DECstation platform!!! (0 replies, 04/11/91)

RFD: comp.lsi.testing (0 replies, 04/11/91)

Looking for PD ATPG. (0 replies, 04/15/91)

Viewer for Spice, ESIM, RNL, HILO, and CAZM (0 replies, 04/15/91)

GDS2 parser (0 replies, 04/19/91)

EDIF data (2 replies, 04/19/91)

MPLA tech. files for the latest MOSIS design rules (0 replies, 04/19/91)

DAC '91 - Online information (0 replies, 04/19/91)

Info Needed on More, Difficult Examples for Global Router (0 replies, 04/21/91)

Actel/WorkView Simulation Problem (0 replies, 04/23/91)

Question: anyone knows the address/phone # of the company (0 replies, 04/23/91)

PCAD schematic capture (0 replies, 04/24/91)

EDIF Parser (3 replies, 04/24/91)

Conference on VLSI Design (0 replies, 04/24/91)

NSF Faculty Workshop on Electronic Design Automation (0 replies, 04/24/91)

Sigview Documentation Update (0 replies, 04/24/91)

router effeciency (2 replies, 04/25/91)

Wanted: MAGIC Source Code (0 replies, 04/26/91)

1st CFV: comp.lsi.testing (0 replies, 04/27/91)

MOSIS Email Address (0 replies, 04/29/91)

Want cell level (1 reply, 04/30/91)

Questions for chipmunk (0 replies, 04/30/91)

Mixed level extraction and verification (0 replies, 04/30/91)

CFP: Defect and Fault Tolerance (0 replies, 04/30/91)

Product Data Management systems (0 replies, 04/30/91)

CFP: Defect and Fault Tolerance Workshop (0 replies, 04/30/91)

ViewLogic WorkView Bus Problem (0 replies, 05/01/91)

CFV: comp.lsi.testing (0 replies, 05/01/91)

Magic ported on IBM-PC? (1 reply, 05/03/91)

Porting cifplot (0 replies, 05/04/91)

THE THIRD PHYSICAL DESIGN WORKSHOP (0 replies, 05/05/91)

ISCAS-85 benchmark circuits...Is layout available?? (0 replies, 05/05/91)

New Book Announcement: The Art of Computer Systems Performance Analysis (0 replies, 05/05/91)

ATPG D-alg need source (0 replies, 05/06/91)

VLSI 91 Conference (0 replies, 05/06/91)

DRAM Model for WorkView?? (0 replies, 05/07/91)

looking for MIS (0 replies, 05/07/91)

looking for MAMBO (0 replies, 05/07/91)

Free CAD Utility Tools (0 replies, 05/07/91)

Wanted: CAD software / designed objects (0 replies, 05/08/91)

spice3d2 crashes in help commands and set unixcom (0 replies, 05/09/91)

CHDL 91 Proceedings - BibTeX file (0 replies, 05/09/91)

The Spice3d2 on DECstation 3100/X11R4 (0 replies, 05/09/91)

28th ACM/IEEE Design Automation Conference - June 17-21, 1991 (0 replies, 05/10/91)

Symbolic simulation/abstract execution of proderal languages (0 replies, 05/11/91)

CIF -> PostScript? (0 replies, 05/11/91)

X windows based kic (1 reply, 05/14/91)

Looking for PC board layout tools for Sun or Mac (0 replies, 05/14/91)

Magiv V6 (0 replies, 05/15/91)

Looking for Magic and Spice distributions (0 replies, 05/15/91)

Reqd: Device simulators suggestions (0 replies, 05/16/91)

ATPG refs, eps. Parallel versions (0 replies, 05/17/91)

Looking for def (0 replies, 05/17/91)

Summary of PCB layout & Schematic Capture for Mac/Sun (0 replies, 05/20/91)

OCT5.0 Netlist Question (0 replies, 05/20/91)

updated list of Magic notes (0 replies, 05/21/91)

Anybody interested in a PD-testpattern generator (0 replies, 05/21/91)

CAD/CAM modeling to manufacturing <---- how much is automated??? (0 replies, 05/22/91)

Cheap silicon processing (3 replies, 05/23/91)

RESULT: comp.lsi.testing passes 178: 31 (0 replies, 05/23/91)

parallel spice (0 replies, 05/23/91)

ascii --> trascii --> sentry tape (1 reply, 05/24/91)

Wanted: Chipmunk (0 replies, 05/25/91)

3.3V v/s 5V (2 replies, 05/26/91)

TSC checkers (1 reply, 05/27/91)

logic synthesis tools (2 replies, 05/29/91)

EDA / Framework surveys ? (0 replies, 05/30/91)

MOSIS Service (0 replies, 05/30/91)

logic mimimisation (0 replies, 05/30/91)

Calma Plotting (0 replies, 05/31/91)

Problem with magic under Openwindows and twm (0 replies, 06/02/91)

Parks-McClellan FIR filter design (0 replies, 06/02/91)

SPICE (1 reply, 06/03/91)

Quickturn Article Available (0 replies, 06/03/91)

Need references to some HDL's (3 replies, 06/05/91)

Versatec plotter paper (0 replies, 06/08/91)

syntax for literals in nutmeg (0 replies, 06/11/91)

Autocad with HiPad Plus digitizer (0 replies, 06/11/91)

ChipGraph to Gerber interface wanted (0 replies, 06/12/91)

HEMT device modelling (0 replies, 06/14/91)

What is the latest version of EDIF and is there an update coming ? (1 reply, 06/15/91)