manley@optilink.UUCP (Dave Manley) (09/18/90)
Has anyone out there had personal experience with these tools and
could they comment on the following points:
Do (can) the placement tools use the hierarchical netlist to obtain a
better placement than is available from the flattened netlist? I
assume the extra information in the hierarchical netlist could be
used to do this?
How are the net 'weights' used by the router? Do the nets with
higher weights get routed first? The weights are not in the flattened
netlist - why?
What routing strategies does the router use?
What experience have you had with the larger gate arrays (>40
raw gates) with regards to utilization.
What problems, if any have you had with clock skew in the clock
distribution tree?
Any information on any of these subjects would be welcomed.
Thanks in advance,
**************************************************
* Dave Manley
* Optilink Corporation
* Petaluma, CA
* 707-795-9444
*
* {uunet|pyramid}!optilink!manley
**************************************************manley@optilink.UUCP (Dave Manley) (09/18/90)
In article <4470@optilink.UUCP>, manley@optilink.UUCP (Dave Manley) writes: > What experience have you had with the larger gate arrays (>40 gates) > with regards to utilization. > One of my fellow workers suggests that 40 gates isn't all that much. So let me try again... Our actual gate counts are in the 15k-25k gate range which puts us into 46k to 77k gate devices. Thanks again, ************************************************** * Dave Manley * Optilink Corporation * Petaluma, CA * 707-795-9444 * * {uunet|pyramid}!optilink!manley **************************************************
dgreen@ibm.com (Dan R. Greening) (09/18/90)
manley@optilink.UUCP (Dave Manley) writes: |> Has anyone out there had personal experience with these tools and |> could they comment on the following points: |> |> Do (can) the placement tools use the hierarchical netlist to obtain a |> better placement than is available from the flattened netlist? I |> assume the extra information in the hierarchical netlist could be |> used to do this? Some commercial tools do use the hierarchy to help place the circuits. I believe that Seattle Silicon's product, for example, does this. However, it isn't all that clear that using the hierarchy necessarily helps. In some cases, yes. In others, no. I believe this is an open research area. The following reference may provide some help, in itself, through its reference list, or through references to it (see Scientific Citation Index in a good science library). J. Rose, W. Klebsch and J. Wolf, Temperature Measurements and Equilibrium Dynamics of Simulated Annealing Placements, IEEE Transactions on CAD, v 9, n 3 (March 1990) p 253-259. Dan Greening 12 Foster Court NY (914) 784-7861 dgreen@cs.ucla.edu Croton-on-Hudson, NY 10520 CA (213) 825-2266
moss (Barry Moss) (09/18/90)
In article <4470@optilink.UUCP> manley@optilink.UUCP (Dave Manley) writes: >Has anyone out there had personal experience with these tools and >could they comment on the following points: > >Do (can) the placement tools use the hierarchical netlist to obtain a >better placement than is available from the flattened netlist? I >assume the extra information in the hierarchical netlist could be >used to do this? > I have recently completed a 2.3K gate array design with Oki logic using Valid Logic's GED schematic capture. Valid "flattens" the design as part of the compilation of the netlist. Looking at some of the reports that Oki produces, it would appear that their system performs a net list translation without regard to the hierarchical netlist names; therefore, I would assume that their router does not use heirarchical information to produce a better placement. Just one person's experience. Barry Moss Design Engineer Mobile Data International (A Motorola Company)
sss@ole.UUCP (Stephen Sugiyama) (09/20/90)
dgreen@cs.ucla.edu writes: > manley@optilink.UUCP (Dave Manley) writes: > > |> Has anyone out there had personal experience with these tools and > |> could they comment on the following points: > |> > |> Do (can) the placement tools use the hierarchical netlist to obtain a > |> better placement than is available from the flattened netlist? I > |> assume the extra information in the hierarchical netlist could be > |> used to do this? > > Some commercial tools do use the hierarchy to help place the circuits. > I believe that Seattle Silicon's product, for example, does this. Well, not exactly. The Seattle Silicon tools (which are cell-based, not for gate arrays) work off of a flattened netlist, except that tool-specific cells (Datapath, e.g.) are partitioned based on inherited properties from the schematic. I think Dave Manley was asking specifically about the gate array tools from VLSI Technology: I don't know the details of their tools (hi Sunil) but I suspect that their "Gate Assistant" floorplanning tool uses hierarchy to define blocks. I doubt that any further hierarchy information is used in the placement. > However, it isn't all that clear that using the hierarchy necessarily > helps. In some cases, yes. In others, no. This is a good point; also note that a "better placement" doesn't nessarily mean one that is smaller in area. -- Stephen Sugiyama ...uw-beaver!sumax!ole!sss ole!sss@beaver.cs.washington.edu
bhoughto@cmdnfs.intel.com (Blair P. Houghton) (09/20/90)
In article <1990Sep18.151012.1177@arnor.uucp> dgreen@cs.ucla.edu writes: >manley@optilink.UUCP (Dave Manley) writes: >|> Do (can) the placement tools use the hierarchical netlist to obtain a >|> better placement than is available from the flattened netlist? I >|> assume the extra information in the hierarchical netlist could be >|> used to do this? > >However, it isn't all that clear that using the hierarchy necessarily >helps. In some cases, yes. In others, no. It helps. The least it does is improve critical-path; often it also aids the place-n-route tool by removing a big chunk of its placement choices. [Dan's ref:] > J. Rose, W. Klebsch and J. Wolf, Temperature Measurements and > Equilibrium Dynamics of Simulated Annealing Placements, IEEE > Transactions on CAD, v 9, n 3 (March 1990) p 253-259. > >Dan Greening 12 Foster Court NY (914) 784-7861 >dgreen@cs.ucla.edu Croton-on-Hudson, NY 10520 CA (213) 825-2266 Check out also Fiduccia, C. M., and Mattheyses, R. M., "A Linear-Time Heuristic for Improving Network Partitions", Proc 19th IEEE Design Automation Conference (DAC), 1982, pp175ff. The references in that paper cite some stuff Kernighan and Lin did at Bell Labs in the very early '70s. --Blair "...bigger, stronger, faster."