holmer@ernie.Berkeley.EDU (Bruce K. Holmer) (09/21/90)
The following is a set of Unix command lines (and small awk programs)
that I have found helpful in checking a layout for unconnected nodes
(a typical error in hand layout). These scripts assume a CMOS sim
file with no aliases (our layout CAD tools can generate this
directly). For those of you who have an alias file after extraction,
you would need to preprocess the sim file to substitute a unique name
for each node.
I'd be interested in finding out if there are more sophisticated tools
for discovering typical layout errors (either using Magic or sim as
input).
Enjoy,
--Bruce
----------------------------------------------------------------------
First gather only the n and p lines of the sim file:
egrep '^[np]' design.sim | ... (continued below)
Rearrange the order of the source and drains fields to canonicalize
the transistor listing. Then remove duplicate transistors and move
transistor pairs that make up inverters to adjacent lines:
... | awk -f canonical.awk | sort -u +1 +0 | ...
%%%%%%%%%%%%%%%%%%%% canonical.awk %%%%%%%%%%%%%%%%%%%%
{if (($3== "GND" && $4 != "Vdd") || $3 == "Vdd" || \
($4 < $3 && $4 != "GND" && $4 != "Vdd")) print $1,$2,$4,$3;
else print $1,$2,$3,$4;}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Now find the n and p that makes up each inverter and replace them with
the line "inv input_node output_node":
... | awk -f find_inv.awk > design.inv
%%%%%%%%%%%%%%%%%%%% find_inv.awk %%%%%%%%%%%%%%%%%%%%
BEGIN {getline;
o1 = $1; o2 = $2;
o3 = $3; o4 = $4;}
($1 == "p") && ($4 == "Vdd") {if (o1 == "n" && o4 == "GND" && \
o2 == $2 && o3 == $3) {
print "inv", $2, $3;
getline;
o1 = $1; o2 = $2;
o3 = $3; o4 = $4;
next;}}
{print o1, o2, o3, o4;
o1 = $1; o2 = $2;
o3 = $3; o4 = $4;}
END {if (o1 != "") print o1, o2, o3, o4;}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Collecting the fragments, the command line is:
egrep '^[np]' design.sim | awk -f canonical.awk | sort -u +1 +0 | \
awk -f find_inv.awk > design.inv
Now we can look for unconnected nodes. The first thing we'll look for
is any node name that occurs just once:
awk '{print $2; print $3; if ($1 != "inv") print $4}' design.inv | \
sort | uniq -u > single.occurrence.nodes
The second test is to find all node names that appear only on
transistor gates (input pad nodes may be included):
awk '{print $2}' design.inv | sort -u > gates
awk '{print $3; if ($1 != "inv") print $4}' design.inv | \
sort -u > srcdrns
comm -23 gates srcdrns > gate.only.nodesshers@masala.lcs.mit.edu (Alexander The Great) (09/22/90)
In article <38779@ucbvax.BERKELEY.EDU> holmer@ernie.Berkeley.EDU (Bruce K. Holmer) writes: # #The following is a set of Unix command lines (and small awk programs) #that I have found helpful in checking a layout for unconnected nodes #(a typical error in hand layout). These scripts assume a CMOS sim #file with no aliases (our layout CAD tools can generate this #directly). For those of you who have an alias file after extraction, #you would need to preprocess the sim file to substitute a unique name #for each node. # #I'd be interested in finding out if there are more sophisticated tools #for discovering typical layout errors (either using Magic or sim as #input). # #Enjoy, #--Bruce # This code is a nice thing to keep around, but using the switch level simulator while debugging the logic (digital chips only, of course) catches these unconnected nodes as well. Alex -- +-------------------------------+------+-----------------+---------------------+ |Alexander The Great Sherstinsky|me |shers@caf.mit.edu|To become as refined | |Alexander Semyon Sherstinsky |myself|shers@caf.mit.edu|a person as possible.| |Alex Sherstinsky |I |shers@caf.mit.edu|*********************|
holmer@ernie.Berkeley.EDU (Bruce K. Holmer) (09/22/90)
In article <1990Sep21.232209.28404@mintaka.lcs.mit.edu> shers@masala.lcs.mit.edu (Alexander The Great) writes: >This code is a nice thing to keep around, but using the switch level simulator >while debugging the logic (digital chips only, of course) catches these >unconnected nodes as well. You are absolutely correct. The principal time to use the scripts is just after layout has completed and before switch level simulation starts in earnest. The chip we designed has 110,000 transistors and took overnight to reextract. The first run of the scripts found 137 unconnected wires. This saved us several days of tracing back X's in esim and reextraction. However, we spent weeks tracing down other errors: wrong gates, missing inverters, extra inverters, swapped wires, bus contention, etc. So the conclusion is that the scripts save a small but non-trival amount of time. I forgot to mention in the original article that sort uses /tmp to store intermediate results. If you have a big chip, /tmp may not have enough room. Use sort's -T option to get around this. --Bruce