carpent@SRC.Honeywell.COM (Todd Carpenter) (06/07/90)
I am currently involved in a tradeoff of VHDL vs. Verilog. Specifically, we are examining Vantage Analysis Systems's VHDL, and Cadence's Verilog products. Any data which would aid the decision would be greatly appreciated. Views from both sides of the fence are welcome, especially any data from someone who has already made such a tradeoff or has experience with both environments. The project for which we are doing the trade involved ASIC chip design. We will be using a top down design methodology covering abstract behavioral models down to detailed gate design. Other tools, such as Mentor, might be more appropriate at the lower levels. Data specifically of interest: Language Features Tool Features Schematic Entry Symbolic Debugger Compiler Results/Output Interface to other tools Library Management Links to synthesis tools (e.g., Synopsis) Performance Ease of use Compiler Speed Runtime Speed Design iteration speed Learning curve for language Learning curve for tools Platform stability Vendor support Thank you *VERY* much. I will forward a compilation of responses, or post if there is sufficient interest. Please email responses to: carpent@src.honeywell.com {I know a similar question came by a month ago. However, I did not see any answers to these questions, aside from some useful VHDL references. Would it be more appropriate to post in comp.lsi.cad, or comp.lsi?} -Todd C. Todd P. Carpenter Honeywell Systems and Research Center voice: (612)782-7229 paper: 3660 Technology Drive, Minneapolis, MN 55418 UUCP: carpent@srcsip.uucp bang-style: {umn-cs,ems,bthpyd}!srcsip!carpent Internet: carpent@src.honeywell.com