[comp.lsi.cad] Need guidance using Octtools 4.0 to create a dual ported register file

paul@cronus.m2c.org (Paul Cohen) (02/07/91)

In article <445@feith1.UUCP>, john@feith1.UUCP (John L. Wehle) writes:
|> Hello,
|> 
|> I need some guidance on using octtools to create a dual ported register file.
|> I am trying to create a 28 deep by 8 bit wide dual ported register file
|> using Octtools 4.0.  My first step was to create a dual ported bit register.
[ lots of info deleted ]

First of all, you shouldn't be using the dlm library anymore. Use
the stdcell2_2 library with Octtools 4.0. The layout of the new cells is
much cleaner, and you'll get much better results from fab.

Now for your question. Wolfe is intended for fixed height, variable width
cells, and you're trying very hard to defeat what wolfe wants to do.
Even though wolfe finished with the 8 bit reg, if you take a close look
you'll find out that it isn't correct. There are non-manhattan wires
on Vdd. This is because you are giving wolfe different cell heights 
(the register and the 2 dlm cells). The height of the register cell 
includes the wiring added by wolfe. In addition, you're beginning to
get redundant Vdd and ground connections at the ends of the row of
cells. (Take a look in Vem.)


I'd approach it in one of two ways. 

1) Assemble the logic, without doing intermediate placements, 
then do a place and route on the whole thing at the end.

So, the flow would look like:

bdnet dp_bit_reg.bdnet
bdnet dp_8_bit_reg.bdnet
bdnet smallreg.bdnet
octflatten -t LEAF -o smallreg:leaf smallreg:logic
wolfe -o smallreg:placed smallreg:leaf

2) If you really want 28 rows, then I'd make the rows then use
mosaico, which can route arbitrary blocks.

bdnet dp_bit_reg.bdnet
bdnet dp_8_bit_reg.bdnet
wolfe -r1 ...
bdnet smallreg.bdnet  [but add placement information to the instance]
mosaico -c -o smallreg:placed smallreg:logic

Either way ought to work.


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