ruthl@mcnc.org (Alice Ruth Lorenzetti) (04/12/89)
International Workshop on Logic Synthesis
Research Triangle Park, North Carolina, USA
May 23-26, 1989
Sponsored by the Microelectronics Center of North Carolina (MCNC)
In Cooperation with
ACM Association for Computing Machinery
_______________________________________________________________________________
Preliminary Program
Tuesday Evening, May 23:
4:30-8:30 p.m. Registration (Holiday Inn)
6:30-9:30 p.m. Reception and cocktails (Holiday Inn)
Wednesday, May 24:
7:45-8:30 a.m. Continental Breakfast (Holiday Inn)
8:30-8:45 a.m. Introduction
Franc Brglez, Workshop Chairperson,
Bell-Northern Research
Matt Kuhn, President, MCNC
Alberto Sangiovanni-Vincentelli,
Technical Program Chairperson,
University of California-Berkeley
8:45-10:30 a.m. Session 1: Multi-level Optimization I
Chairperson: Gary Hachtel, University of Colorado
1.1 Two Fast Two-Level Minimizers for Multi-Level
Logic Synthesis, H. Savoj, M. Malik, R. Brayton,
University of California-Berkeley
1.2 OPAM: An Efficient Output Phase Assignment for
Multilevel Logic Minimization, C-L Wey, S-M Chang,
Michigan State University
1.3 Experiments with Global-Flow Analysis,
S . Parkes, R. Saleh, University of Illinois;
R. Rudell, Synopsys, Inc.
10:30-11:00 a.m. Break
11:00-12:45 p.m. Session 2: Introduction of Synthesis Benchmarks
Chairperson: Robert Lisanke, MCNC
This session will be organized by May 5th.
12:45-1:30 p.m. Lunch (Holiday Inn)
1:30-4:00 p.m. Session 3: Don't Care Conditions in Logic Synthesis
Chairperson: Robert Brayton, University of
California-Berkeley
3.1 On the Relationship Between Area Optimization and
Multifault Testability of Multilevel Logic, G. Hachtel,
R. Jacoby, C. Morrison, University of Colorado;
K. Keutzer, AT&T Bell Laboratories
3.2 The Satisfiability Don't Care Set and Invariant
Transformations in Multi-Level Synthesis, P. McGeer,
R. Brayton, University of California-Berkeley
3.3 On Computing and Approximating the Observability
Don't Care Set, G. Hachtel, R. Jacoby, P. Moceyunas,
University of Colorado
3.4 Boolean Relations, R. Brayton, University of
California-Berkeley; F. Somenzi, SGS-Thompson
4:00-5:15 p.m. Break/Posters
Poster presentations will be organized by May 5.
5:15-6:30 p.m. Session 4: Synthesis Systems
Chairperson: Louise Trevillyan, IBM, Corp.
4.1 BESTMAP: Behavioral Synthesis From C., J-Y Jou, S.
Rothweiler, R. Ernst, S. Sudawala, A. Prahbu, D. Tsao,
M. Lega, AT&T Bell Laboratories
4.2 A Unified Logic Synthesis System: ZEPHCAD,
H. Sato, Fujitsu, Ltd.
6:30 p.m. Reception/Dinner (Holiday Inn)
8:45 p.m. Panel Session 1: Logic Synthesis, Developers
Versus Users Chairperson: Kurt Keutzer, AT&T
Bell Laboratories
Panelists to be announced
Thursday, May 25:
7:45-8:45 a.m. Continental Breakfast (Holiday Inn)
8:45-10:30 a.m. Session 5: Sequential Logic Synthesis
Chairperson: Tsuguo Shimizu, Central Research
Laboratory
5.1 Retiming and Resynthesis: Optimizing
Sequential Networks with Combinational
Techniques, S. Malik, E. Sentovich, R. Brayton,
University of California-Berkeley
5.2 Synchronous Logic Synthesis, G. De Micheli,
Stanford University
5.3 Restructuring State Machines and State Assignment:
Relationship to Minimizing Logic Across Latch
Boundaries, B. Lin, A Newton, University of
California-Berkeley
10:30-11:00 a.m. Break
11:00-12:45 p.m. Session 6: Control Synthesis
Chairperson: Daniel Gajski, University of
California-Irvine
6.1 Race-Free Time-Optimised Synthesis of Asynchronous
Interface Circuits, P. Vanbekbergen, F. Catthor,
H. DeMan, IMEC Lab; J. Van Meerbergen, Philips
Research Labs
6.2 A New Embedding Method for State Assignment,
F. Piorot, VLSI Technology; G. Saucier, C. Duff,
Laboratoire CSI/INPG
6.3 Finite State Machine Synthesis Using Shadow
States, R. Graham, Silc Technologies
12:45-1:30 p.m. Lunch (Holiday Inn)
1:30-3:15 p.m. Session 7: Logic Decomposition
Chairperson: N. F. Benschop, Philips Research
7.1 Viable Logic Synthesis Tools Using Transform
Methods, D. Varma, E. A. Trachtenberg, Drexel
University
7.2 Synthesis of Multilevel Networks with
Simple Gates, X. Xiang, S. Muroga,
University of Illinois
7.3 Logic Minimization for Factored Forms, A. Malik,
R. Brayton, A. Sangiovanni-Vincentelli, University of
California-Berkeley
3:15-4:45 p.m. Break/Posters
Poster presentations will be organized by May 5.
4:45-6:30 p.m. Session 8: Multi-Level Optimization II
Chairperson: Fabio Somenzi, SGS-Thompson
8.1 PLA-Based Synthesis Without PLA's, D. Brand,
IBM Corp.
8.2 Technology Mapping for Delay, R. Rudell,
Synopsys, Inc.
8.3 Redundancy Identification and Removal,
D. Bryan, F. Brglez, R. Lisanke, Microelectronics
Center of North Carolina
6:30 p.m. Reception/Dinner (Holiday Inn)
8:45 p.m. Panel Session 2: Research Issues in the 90's
Chairperson: Alberto Sangiovanni-Vincentelli,
University of California-Berkeley
Panelists to be announced
Friday, May 26:
7:45-8:45 a.m. Continental Breakfast (MCNC)
8:45-10:30 a.m. Session 9: Encoding
Chairperson: Giovanni De Micheli, Stanford University
9.1 Algorithms for State Assignments of Finite State
Machines for Optimal Two-Level Logic Implementations,
T. Villa, A. Sangiovanni-Vincentelli, University
of California-Berkeley
9.2 A Generalized PLA Decomposition with Programmable
Encoders, S. Yang, M. Ciesielski, University of
Massachusetts
9.3 Encoding Symbolic Inputs for Multi-Level Logic
Implementation, S. Malik, R. Brayton,
A. Sangiovanni-Vincentelli, University of
California-Berkeley
10:30-11:00 a.m. Break
11:00-12:15 p.m. Session 10: Complexity Issues
Chairperson: Richard Rudell, Synposis, Inc.
10.1 Computational Complexity of Logic Synthesis and
Optimization, K. Keutzer, University of
California-Berkeley; D. Richards, University of
Virginia
10.2 On the Complexity of Three-Level Logic Circuits,
T. Sasao, Kyushu Institute of Technology
12:15-1:00 p.m. Session 11: Short Papers
Chairperson: Richard Rudell, Synposis, Inc.
11.1 Communication Complexity Driven Logic Synthesis,
T-T Hwang, R. Owens, J. Irwin, Pennsylvania State
University
11.2 Min-Cut Algorithm for State Coding, N. Benschop,
Philips Research Labs
11.3 Technology Mapping for Sequential Logic
Synthesis, C.W. Moon, B. Lin, H. Savoj, R. Brayton,
University of California-Berkeley
1:00 p.m. Lunch (MCNC) and optional MCNC tour
Depart for airport (shuttles from MCNC)
________________________________________________________________________________
For further information contact:
Local Arrangements Chairperson:
Ruth Lorenzetti
MCNC
3021 Cornwallis Road
P.O. Box 12889
RTP, NC 27709-2889
Phone: 919-248-1923
Email: ruthl@mcnc.org
____________________________________________________________________________
International Workshop on Logic Synthesis
Research Triangle Park, North Carolina, USA
May 23-26, 1989
BENCHMARK SUMMARY
In the past, researchers expressed interest in having a set of
standard benchmarks that could be used to evaluate the quality of
various logic synthesis methods. We have, therefore, collected
logic descriptions from individuals who are willing to have their
examples redistributed. The logic synthesis and optimization
benchmark set consists of examples from three broad categories:
-Two-level logic in PLA (ESPRESSO) format.
-Finite-state tables in KISS or ESPRESSO-MV format.
-Multi-level logic in BLIF or Netlist-BLIF format.
Both the benchmark examples and accompanying documentation are
available from MCNC (see below).
Presentation of Benchmark Results
The workshop will hold a special poster session for presentation
of results based on the logic synthesis benchmarks.
If you wish to participate in the benchmark poster session,
please indicate this on your workshop registration form or notify
Ruth Lorenzetti, Publicity/Arrangements Chair, at (919) 248-
1923.
The poster session registration deadline is May 5, 1989.
To participate in the benchmark poster session, your results
should be suitable for display on a 32 x 40 in. (81.3 x 101.6
cm.) or a 40 x 60 in. (101.0 x 52.4 cm.) poster board. You may
choose either size to display your results. We will provide the
poster board as well as transparent tape and pins to help you
mount your material. Please keep in mind the need for large
lettering so that your results can be viewed easily.
Benchmark Distribution
The benchmark examples for the 1989 International Workshop on
Logic Synthesis can be obtained from MCNC in two ways.
You may establish an FTP connection to host "mcnc.org" or
"mcnc.mcnc.org" and copy the files using the mget command. The
login name is "anonymous" and the password is "guest". The files
are under the "/pub/benchmark/synth89/" directory.
Check the FTP man page for details. The following command se-
quence will obtain all the benchmark data contained in subdirec-
tories: fsmexamples (FSMs), twolexamples (two-level examples in
ESPRESSO format), mlexamples (multi-level "BLIF" examples),
wkslibrary (the workshop libraries to be used for synthesis), and
wksdoc (benchmark document in ASCII and LaTeX form).
(FTP command sequence)
ftp mcnc.org
(or ftp mcnc.mcnc.org)
anonymous (in response to the "Name" prompt)
guest (in response to the "password" prompt)
cd pub/benchmark/synth89
cd fsmexamples
mget *
cd ../mlexamples
mget *
cd ../twolexamples
mget *
cd ../wkslibrary
mget *
cd ../wksdoc
mget *
bye
We are also prepared to send you a 9-track tape in either TAR
format or VMS format. Contact us about your requirements. We
are requesting that ACM SIGDA provide funds to cover the cost of
tapes and shipping, so there is no cost to you for this service.
For more detailed information about these benchmarks, you may
contact Bob Lisanke at (919) 248-1442; e-mail bob@mcnc.org or Tom
Krakow, Benchmark Archival Secretary, (919) 248-1959; email
krakow@mcnc.org.