[comp.lsi.cad] router effeciency

ram@shukra.Eng.Sun.COM (Renu Raman) (04/21/91)

We have some outside routers and some inhouse routers and am trying to
compare the relative effeciency of these routers.  One layman metric is
router efficiency which has been defined in atleast 2 different ways. I 
would like to know what is the common understand of it

  (This is mostly related to chip routers - specifically block routers)

  a) router efficiency: Ratio of routed area to total core area (where
     total core area is die size minus pad rings)
  b) router efficiency: Ratio of routed area to total block areas
     where block areas is sum of areas of the blocks in the core (not pad)

GIven (a) or (b) - first tell me which one is the correct one and then 
would like to know - what are the numbers for custom chips (probably manual)
semi-custom chips (using automatic block routers) for dice in the 12-15mm
range?

Thanks

renu raman
--
--------------------------------
   Renukanthan Raman				ARPA:ram@sun.com
   M/S 16-11, 2500 Garcia Avenue,               TEL :415-336-1813
   Sun Microsystems, Mt. View,  CA 94043

sss@ole.UUCP (Stephen Sugiyama) (04/22/91)

In article <11963@exodus.Eng.Sun.COM> (Renu Raman) writes:
> We have some outside routers and some inhouse routers and am trying to
> compare the relative effeciency of these routers.  One layman metric is
> router efficiency which has been defined in atleast 2 different ways. I 
> would like to know what is the common understand of it
> 
>   (This is mostly related to chip routers - specifically block routers)
> 
>   a) router efficiency: Ratio of routed area to total core area (where
>      total core area is die size minus pad rings)
>   b) router efficiency: Ratio of routed area to total block areas
>      where block areas is sum of areas of the blocks in the core (not pad)
> 
> GIven (a) or (b) - first tell me which one is the correct one and then 
> would like to know - what are the numbers for custom chips (probably manual)
> semi-custom chips (using automatic block routers) for dice in the 12-15mm
> range?

Well, I think router efficiency numbers are almost always suspect, and
here are a couple of reasons why:

1.  The efficiency (at least as you've defined it) is design
    dependent.  A design with two large blocks and two nets is going to
    have an efficiency approaching one.  A design with two small blocks
    and, say, 500 nets will have an efficiency approaching zero.

2.  Routers are very placement dependent.  Different placements will
    cause the same router to produce different results for the same
    design.  One router may perform better than another router on one
    placement, but on a different placement the reverse will be true.
    You can't separate routing from placement.

>    Renukanthan Raman				ARPA:ram@sun.com
>    M/S 16-11, 2500 Garcia Avenue,               TEL :415-336-1813
>    Sun Microsystems, Mt. View,  CA 94043

There are many other reasons why it is difficult to evaluate routers,
but I won't go into them here.  Are you familiar with the MCNC layout
benchmarks?  Krzysztof Kozminski will be discussing their status in a
paper at the 1991 Design Automation Conference.

I hope that this is somewhat helpful.
-- 
Stephen Sugiyama
ole!sss@sumax.seattleu.edu

hardaker@iris.UCDavis.EDU (Wes Hardaker) (04/25/91)

I too am interested in estimating the output size of place & route
routines.  Currently, I am using lager to do some auto-matic place &
route, and I would really like to get a general estimate of the final
layout size before actually spending x number of hours to do the routing
only to discover it is too large to use.  Is there any references to
this at all in journals, etc. that I can browse through (ANY router, not
just lager).

Obviously, as somone pointed out earlier, it is not possible to get an
extremely accurate estimate, but even a rough estimate would be nice!
                                                                _____
							       / ___ \
Wes Hardaker					       	      / /   \/
Department of Electrical Engineering and Computer Science    \--/     /\
University of California at Davis	 __________________   \/     /--\
(hardaker@eecs.ucdavis.edu)             /     Recycle      \    /\___/ /
                                       / It's not too late! \   \_____/