watt@eleazar.dartmouth.edu (Gill Watt) (04/03/91)
howdy, I don't know if anyone out there can help me, but if you can it would be great. We have the Actel Action Logic System (ALS) (Release 1.22) FPGA design software running on a PC here. It works very well except for one annoying problem, there seems to be no way to save/print (record in any way) the results from the timing analysis. At the moment, in order to compare different designs, I am reduced to typing the data into a spreadsheet on my mac in order to print it out. There has to be a better way. Please help. -- --------------------------------------------------------------------- Gill Watt (watt@eleazar.dartmouth.edu) Thayer School of Engineering, Dartmouth College, Hanover, NH 03755 ---------------------------------------------------------------------