steveg@cadence.com (Steven Greenberg; x6231) (01/19/91)
In "computer Design Aids for VLSI Circuits" edited by P. Antognetti, D.O. Pedersen, and H. DeMan, published by Sijthoff & Noordhoff 1981, NATO Advanced Study Institute Series, there is a relevant chapter. It is capter 2 by A. L. Sangiovanni-Vincentelli, "Circuit Simulation". Page 108 has a typical histogram of where Spice spends its time. I believe this data is derived from "Analysis Time, Accuracy, and Memory Requirement Tradeoffs in SPICE2", by A. R. Newton and D. O. Pederson, in the Proceedings Asilomar Conference, 1978. I could swear that Newton published this in an IEEE journal, but I just can't come up with it quickly. Briefly, for circuits of less than say 1000 nodes or transistors, 90% or more of SPICE's time is spent in evaluating device models and loading them into the matrix. Since the time spent doing this is linear in the number of transistor, but the time spent factoring the matrix rises as the 1.2 to 1.5 power of the number of nodes, eventually the time spent in matrix solution will dominate as the circuit grows larger. /Steve