pjd@demon.siemens.com (dr. funk) (11/13/90)
Here are the responses received to my previous inquiry about transmission gate simulation in irsim. The two questions were: 1. Does irsim have known problems with T-gates? 2. Are there rules (work-arounds) for irsim T-gates? Thanks, gentlemen and thanks to Alex for contributing SLIC. Software pack-rat that I am, I have a copy, but have not yet installed it and tried it out on the circuit in question. ***************** I don't know about irsim, but in the predecessor (rsim), problems such as you describe often resulted from charge-sharing or drive fight. Simulators are often improperly blamed for timing errors in the design. Remember that the nMOS and pMOS halves of the t-gate are delayed with respect to one another, and that a t-gate multiplexer may have a sneak path from input to input during the transition. If you sample one of the inputs while the mux is making a transition, you can capture a temporarily corrupted value in a latch. I'd have to see much more detail of your example before blaming irsim. Kevin Karplus karplus@ce.ucsc.edu ***************** I don't have any advice about irsim but I had done something with looking at why a switch level simulator will report X values on certain t-gate circuits and what I found was that the SLS doesn't handle "feedback" very well. It is hard to explain the type of feedback I mean but I identified topologically which circuits (I think) will cause a SLS to report X values. Actually, the circuits that I am speaking of will fail under electrical simulation (SPICE) under certain conditions (tx sizing). I'd be interested in looking at the circuit that failed to see if my identifier (incorporated in a SLS that I wrote) spots the problem. Anyway, hope you resolve your problem. Paul Landsberg paws@vlsi.columbia.edu ***************** The fact that most simulators have difficulty simulating T-gates was one of the reasons that prompted me to write a new switch-level simulator, targetted specifically for T-gate CMOS circuits. It does not have timing (only logic and system timing), but is much simpler to use and requires no user intervention. The name of the simulator is SLIC. All chips simulated with SLIC came back working in first silicon. SLIC uses Berkeley SIM format, just like IRSIM. If you are interested, let me know and I will give you the code. There is no fee, only the obligation to e-mail comments/criticism to the author. Alex Sherstinsky shers@caf.mit.edu -- paul j. drongowski siemens corporate research inc pjd@demon.siemens.com princeton, new jersey 08540 (617) 734-6547