elev26@castle.ed.ac.uk (Gerard A. Allan) (10/26/89)
Double Layer Metal CMOS Circuit Layouts Required.
I would like to determine how efficient CAD design
tools are at producing dense circuit layouts and need exam-
ples of layout from as many different tools as possible. I
would also like to compare the results to hand layout. In
order to do this I require examples of automatically gen-
erated layout and any examples of what could be considered
"good" hand layout. The layout should preferably be in CIF
format, but almost any format will do as we have a number of
conversion programs.
Form a security point of view there maybe a reluctance
to send layout of whole chips, in which case I'd be just as
happy to receive part of a layout (I'm not interested in the
connections to pads or routing). Also there is no need to
provide detail of the circuit function it is sufficient to
say simply ... adder, logic and RAM block etc.
I also guarantee that the design in whole or part will
not be used in any design or fabricated at any time, and
that the design in whole or part will not be transmitted to
any other person.
Could you please state whether the layout was done by
hand or automatically. If automatic layout is sent can you
please say which tool was used.
Thanks in advance for your help
Gerard A. Allan | Post: EMF
gaa@castle.ed.ac.uk | Kings Buildings
JANET:gaa@uk.ac.ed.castle | University of Edinburgh
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