huber@gmdzi.UUCP (Hans Huber) (10/03/89)
THIRD EUROPEAN EDIF FORUM
12, 13 October 1989
Maritim Hotel, Bonn/Koenigswinter, Germany
PRELIMINARY PROGRAMME
Thursday, 12 October 1989 (9.30 - 18.30)
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Heckl, H. (GMD, Germany): Opening
Stanford, P.(Texas Instruments, USA): EDIF Status Report
Session I : EDIF and CAD Frameworks
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(10.00 - 12.30)
Chair: Kahn, H.J., University of Manchester, United Kingdom
Freier, B., Sprenger O., Post, H.U. (Berlin University of Technology, Germany):
EDDB - A Generable VLSI-Design Database with EDIF2 Interface
Koehler, D. (Fraunhofer Working-Group AGD, Germany) -
Redmer, J., Ungerer, M. ( Darmstadt University of Technology, Germany):
Using EDIF for Remote Access to Design Databases: Requirements and Concepts
for an Engineering Remote Database Access
Pieh, O. (Siemens AG, Germany):
Taking Advantage of EDIF in an Advanced Framework Architecture for CAD
Wilkes, W. (University of Hagen, Germany):
DASSY - Data Transfer and Interfaces for Open Integrated VLSI-Design-Systems
- Project Description -
Young, T.C.O. - Kahn, H. J. (University of Manchester, UK):
A Procedural Interface to CAD Data
Abdesslem, M.F. - Bakowski, P. (University of Lille, France):
EDIF Framework Environment for High Exchange Capability
Crowhurst, P.D. - Martin, S.J. (Rutherford Appleton Laboratory, UK):
A Uniform and Simple-to-use Environment for the Development and
Use of EDIF Tools
LUNCH
Session II: Strategic Role of EDIF
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(14.00 -18.30)
Chair: Abel, E., GMD, Germany
Naclerio, N. (EIS / USAF, USA):
Standards for Engineering Information Systems (EIS)
Meys, F.(Philips, Netherland), Chalmers, D. F. (STL, UK)
Successfull CAD Integration Needs a Standard Conceptual Model
Rhyne, T. (CFI /MCC):
Standards within the CAD Framework Initiative
Schroeder, K. Ungerer, M. (Darmstadt University of Technology, Germany):
An Approach to Harmonization of EDIF and STEP
Gravendeel, K., Meys, F., Ranke, G.(Philips, The Netherlands):
STEP and EDIF, Harmonization and Coexistence
Gravendeel, K. (Philips, Netherland):
EDIF in Philips - a User View
Winter, K. (Siemens AG, Germany):
The Integration of EDIF within Siemens: How to Achieve a Real Standard
PANEL: EDIF Exploitations
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Panelists: Cauwenberg, J. (ESPRIT), Gravendeel, K. (Philips), Felix, H. (BULL),
Heaton, J.(ICL), Naclerio, N. (EIS, USAF), Dr. Sauer, A.(Siemens, JESSI/SIGMA),
Dr. Steinmueller, B. (Nixdorf, JESSI/NMP-CADLAB), Rhyne, T. (CFI, MCC),
N.N. (ST)
Moderator: Heckl, H.
"Public " T(S)C & Working Group Meeting
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DINNER (20.00-22.00)
Friday, 13 October 1989 (9.00 - 13.00)
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Session III : Experiences in Using EDIF
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(9.00-10.50)
Chair: Abdesslem, M. F., University of Lille, France
Klein, L. (LPKF CAD/CAM SYSTEME GmbH, Germany):
A Syntax Driven EDIF Editor
Williams, A.; Bell, P.A.; Kahn, H.J. (University of Manchester, UK):
Displaying EDIF Graphical Data: EDDY
Behdjati, A. (Siemens AG, Germany):
Integrating EDIF Data Into a CAD System
Bivas, A. (Daisy/CADNETIX Inc., Israel):
The Development of a Usable EDIF Schematic Reader
Thomson, F., Hughes,G., Marshall, R. (ES2, UK):
EDIF Writers - Practical Experiences within ES2
Angevine, W.; Jonas. S. (Daisy/CADNETIX Inc., USA):
The Magic of ViewMap or How To Do All Sorts of Useful Things with
a Part of EDIF - You May Not Have Known About
Bevan, S.J.; Kahn, H.J., (University of Manchester, UK):
Objectively Parsing EDIF
Huber, H. (GMD, Germany):
Using EDIF for the Transfer of Circuit Diagrams in Electrical Applications
Hunger, A., Gross-Alt, W., Wollschlaeger, G., Dinyarian, F., Mueller. F.
(University of Duisburg, Germany):
Presentation of the Hierarchical Fault Simulator "TESI"
Hilcheson, W. D. (ICL, UK):
Netlist Interchange Including Ripper Cells
Marchetti, E. (Italtel, Italy):
The Use of EDIF Format to Interface Board Design Tools
Marshall, R.A.J., Dente, C. (University of Manchester, UK):
The Capabilities of the EDIF Logicmodel View
Saviotti, L.; Kahn H.J. (University of Manchester, UK):
EDIF - Semantic Checking for Higher Levels
Session IV : Suggestions to EDIF Version 3
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(10.50 - 13.00)
Chair: van Latum, F., Philips, The Netherlands
PANEL: Report on T(S)C activites and EDIF World
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Panelists: Bloedel, J. (TSC Device Modeling & Verifikation), Gravendeel, K.
(TSC PCB), Stanford, P. (TSC Schematic), Wahl, M. (TSC Test), Waters, M.
(EDIF World)
Bloedel, J., Hartenstein, R.W,. (University of Kaiserslautern, Germany):
Extending EDIF for Technology Adaptable Mask Artwork Synthesis
Cathebras, G., Robert, M., Deschacht, D., Auvergne, D. (Lab. Montpellier,
France):
Symbolic Layout Extension to EDIF
Schubert, M., Bloedel, J., Conradi, P., Lafosse, P., Nebel, W., Neusser, S.,
Ryba, M., Schroeder, D. ( Institute for Microelectronic, Stuttgart,
University of Kaiserslautern, University of Hamburg-Harburg, Philips, Germany
and BULL, France):
Extending EDIF for Technology Data
Valvekens, J., Vandeloo, P. (IMEC, Belgium):
Evaluation of EDIF as a Test Specification Format
Walinga, J.S., Peeters, W.F.J., Brombacher, A.C. (Twente University, The
Netherlands):
Algebraic Formula Manipulation Within EDIF
Lafosse, P., Chabaud, J. (BULL, France):
Objects Needed by PCB Modelling in EDIF
Sebesta, W. V. (IBM, USA), Wahl, M. (University of Siegen, Germany):
The State of the EDIF Test Evaluation
La Fontaine, R. (Racal-Redac Systems Ltd, UK):
A Delta Format for EDIF
LUNCH (13.00)