onodera@janus.Berkeley.EDU (Hidetoshi Onodera) (09/12/90)
SASIMI '90
Synthesis And SImulation Meeting
and International Interchange
23rd - 25th October, 1990
Kyoto, Japan
Organization
Advisory Board
Prof. T. Sugano (University of Tokyo)
Dr. H. Mizuno (Matsushita Electric Ind. Co.)
Dr. S. Horiuchi (Matsushita Electric Ind. Co.)
Program Committee
Chairperson
Prof. R.W.Dutton (Stanford University)
Members
Prof. K. Asada (University of Tokyo)
Prof. H. DeMan (IMEC)
Prof. P. B. Denyer (Edinburgh University)
Prof. S. W. Director (Carnegie Mellon)
Prof. A. R. Newton (UC Berkeley)
Prof. G. Saucier (I.N.P.Grenoble)
Prof. I. Shirakawa (Osaka University)
Prof. H.Yasuura (Kyoto University)
Secretary
Dr. T. Akino (Matsushita Electric Ind. Co.)
Program
Oct. 23 (Tue)
Opening ceremony
8:30- 8:40 Welcome greetings by Prof. T. Sugano
8:40- 8:45 Horiuchi
8:45- 9:00 Remarks by the program chairperson, Prof. R. W. Dutton
9:00- 9:15 Coffee break
Logic Synth
[Co-chairpersons : Prof. W. Hahn & Prof. T. Sasao]
9:15-10:15 Invited talk
"Trends and Recent Develo Synthesis"
Prof. R. K. Brayton (UC Berkeley)
10:15-11:15 Ten minute talks by six poster boards
11:15-12:15 Poster boards
(Titles, and Authors)
LS/1 "Logic Synthesis at HP Labs"
Bruce Culbertson, and Barry Shackleford
Hewlett-Packard Lab., California, U.S.A.
LS/2 "Logic Synthesis Expert System Using A Structured Knowledge
Representation"
Noriko Matsumoto, and Tamotsu Nishiyama
Matsushita Elec., Osaka, Japan.
LS/3 "Lexicographical Expression of Boolean Function for Multilevel Synthesis
of High Speed Circuits"
P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, and P. Sicard
Instut National Polytech., Grenoble, France.
LS/4 "Extraction of Arithmetic Functions from Combinational Circuits"
Masahiko Ohmura, Hiroto Yasuura, and Keikichi Tamaru
Kyoto Univ., Kyoto, Japan.
LS/5 "A Class of Logic Function Expressible by Polynomial-Size Binary
Decision Diagrams"
Nagisa Ishiura and Shuzo Yajima
Kyoto Univ., Kyoto, Japan.
LS/6 "Don't Care Set Specification and Computation for Synchronous Digital
Circuits"
Maurizio Damiani, and Giovanni De Micheli
Stanford Univ., California, U.S.A.
12:15-13:30 Lunch
Synthesis from High-Level Descriptions
[Co-chairperson : Prof. G. DeMicheli & Prof. M. Imai]
13:30-14:30 Invited talk
"Computer Aided Design of Real Time Information Processing Systems
: Challenges and Oppotunities"
Prof. H. DeMan(IMEC)
14:30-14:45 Coffee break
14:45-15:45 Ten minute talks by six poster boards
15:45-16:45 Poster boards
(Titles, and Authors)
HL/1 "Efficient State-Assignments for Statecharts"
Doron Drusinsky
SONY Co., Kanagawa, Japan.
HL/2 "Control Logic Synthesis Method Based on Local Behavior Analysis"
Rikako Kuroda, Chihei Miura, and Tsuguo Shimizu
Hitachi Ltd., Japan.
HL/3 "A Study on the Application Specific Microprocessor Design Environment"
Jun Sato, and Masaharu Imai
Toyohashi Univ. of Tech., Aichi, Japan.
HL/4 "Controller State Assignment for Multi-Level Implementation
Based On Cube-Collapsing Constraints"
Gabrielle Saucier, and Christopher Duff
Instut National Polytech., Grenoble, France.
HL/5 "Optimized Synthesis of Large Controllers on a ROM Based Architecture"
Laurent Gerbaux, and Gabriele Saucier
Instut National Polytech., Grenoble, France.
HL/6 "Automata-Theoretic Aids to Scheduling"
Wayne Wolf
Princeton Univ., New Jersey, U.S.A.
Reception
17:30-19:00 Reception
Rump session [Chairperson : Prof. R. W. Dutton]
19:30-21:00 Theme : "High-Level synthesis"
Panel members:
Prof. K. Asada (University of Tokyo)
Prof. H. DeMan (IMEC)
Prof. P. B. Denyer (Edinburgh University)
Prof. O. Karatsu (NTT)
Prof. M. R. Lightner (University of Colorado)
Prof. W. M. C. Sansen (Katholicke University of Leuven)
Oct. 24 (Wed)
Simulation & Verification
[Co-chairpersons : Prof. R. Saleh & Prof. S. Kumagai]
9:00-10:00 Invited talk
"Formal Hardware Verification by Symbolic Simulation"
Prof. R. Bryant (Carnegie Mellon)
10:00-10:15 Coffee break
10:15-11:30 Fifteen minute talks by five poster boards
11:30-12:30 Poster boards
(titles and Authors)
SV/1 "Timing Models for Compiler-Driven Logic Simulation"
W. Hahn, A. Hagerer, M. Eisenhut
Univ. of Passau, Passau, F.R.G.
SV/2 "Behavior Level Simulation of Mixed Level Simulator Melon2"
Masanobu Mizuno, Michiaki Muraoka, and Yuji Takai
Matsushita Elec., Osakaapan.
SV/3 "Coded Time-Symbolic Simulation: Simulation of Logic Circuits with
Nondeterministic Delays Based on Boolean Function Manipulation"
Yutaka Deguchi, Nagisa Ishiura and Shuzo Yajima
Kyoto Univ., Kyoto, Japan.
SV/4 "Fault Simulation for Multiple Faults Using a Shared Binary Decision
Diagrams"
Noriyuki Takahashi, Nagisa Ishiura and Shuzo Yajima
Kyoto Univ., Kyoto, Japan.
SV/5 "Semantic Gap between Hardware Design Languages and Simulators"
Hiroto Yasuura, Koji Tankai and Keikichi Tamaru
Kyoto Univ., Kyoto, Japan.
12:30-13:30 : Lunch
CAD for DSP
[Co-chairpersons : Prof. I. N. Hajj & Prof. M. Kawamata]
13:30-14:30 Invited talk
"Vector Processor Design Using A Hierarchical Behavioral Description
based CAD System"
Dr. N. Ohta (NTT)
14:30-14:45 Coffee break
15:00-16:15 Fifteen minute talks by five poster boards
16:15-17:15 Poster boards
(titles and Authors)
DS/1 "A Software Development System for Digital Signal Processors based on a
Knowledge-Based Retargetable Compiler and a Digital Signal Processing
Language"
Akihiro Hirano, Ichiro Kuroda, Takashi Miyazaki, Takao Nishitani
NEC Co., Kawasaki, Kanagawa, Japan.
DS/2 "CAD Tools for Digital Filter Design"
K. Ikeda, Y. Takenaka, and T. Nishiyama
Matsushita Elec., Osaka, Japan.
DS/3 "CAD System for an Application-Specific DSP Processor Design"
L. G. Chen, L. G. Jeng, K. T. Chao, D. J. Lin, and C. T. Chao
National Taiwan Univ., Taipei, Taiwan.
DS/4 "Pipeline Interleaving Design for FIR, IIR, and FFT"
Yeu-Shen Jehng, Liang-Gee Chen, Tzi-Dar Chiueh, Waiting Chen, and
Her-Ming Jong
National Taiwan Univ., Taipei, Taiwan.
DS/5 "Matching Method for Concurrent Operator, Register and Multiplexer
Allocation"
Anne Mignotte, and Gabriele Saucier
Institut National Polytech., Grenoble, France.
Oct. 25 (Thu)
Design for Testability
[Co-chairpersons : Prof. G. Saucier & Prof. T. Nanya]
9:00-10:00 Invited talk
"Test Pattern Generation using Neural Network"
Prof. H. Fujiwara (Meiji University)
10:00-10:15 Coffee break
10:15-11:15 Fifteen minute talks by four poster boards
11:15-12:15 Poster boards
(titles and Authors)
DT/1 "A SCAN design for asynchronous circuit"
Naoya Chujo, Hiroshi Nagase, and Mitsuharu Takigawa
Toyota Cent. R&D Labs. Inc., Japan.
DT/2 "Design for Testability of ASICs using Sequential ATPG and Automatic
Partial Scan Insertion"
Toshinori Hosokawa, Akira Motohara, Mitsuyasu Ohta, and Toshiro Akino
Matsushita Elec., Osaka, Japan.
DT/3 "Testable Blocking Method for Hierarchical Design of ASICs"
Yasumasa Ueshima, Takashi Mizokawa, and Shigeo Ozawa
Matsushita Elec., Kyoto, Japan.
DT/4 "The Mixed Level Fault Simulation Method of Melon2"
Hiroshi Mizuno, Yukihiro Fukumoto and Michiaki Muraoka
Matsushita Elec., Osaka, Japan.
12:15-13:30 Lunch
Layout Synthesis
[Co-chairpersons : Prof. D. D. Gajski & Prof. S. Tsukiyama]
13:30-14:30 Invited talks
"Timing Driven Layout"
Prof. E. S. Kuh (UC Berkeley)
14:30-14:45 Coffee break
14:45-15:45 Ten minute talks by six poster boards
15:45-16:45 Poster boards
(titles and Authors)
LA/1 "Automatic Module Generator Utilizing Existing Layout Patterns"
Ryoichi Ohe, Koichi Yamashita, Shinji Sato, and Gensuke Goto
Fujitsu Lab., Atugi, Japan.
LA/2 "Multi-Layer Gridless Routing Method Based on Line-Expansion Algorithm"
Naoki Katoh, Masato Mogaki, and Yuriko YamaHitachi Ltd., Tokyo, Japan.
LA/3 "sGAL: A Sea-of-gates Plg System"
Masami Murakata, Masaaki Yamada, Takashi Mitsuhashi, Midori Takano,
Mutsunori Igarashi, Harunori Kadowaki, and Kaori Kora
Toshiba Corp., Kawasaki, Japan.
LA/4 "An algorithm for Power and Ground Routing in Building Block VLSI"
Masahiro Fukui, Yasuhiro Tanaka, Toshiro Akino
Matsushita Elec., Osaka, Japan.
LA/5 "Placement and Global-Wiring Optimization by Trembling Spot-Check"
Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino
Matsushita Elec., Kyoto, Japan.
LA/6 "A Topological Channel Router and Channel Compactor"
Yoshiyuki Kawakami, Koichi Satoh, Masahiko Toyonaga, Toshiro Akino
Matsushita Elec., Osaka, Japan.
LOCAL DETAILS
The workshop will be held at the Conference Hall of the Science Center
Building of the Kyoto Research Park, located in the western part of Kyoto City,
Japan. Hotel accommodations are being arranged close to the Kyoto Research
Park.
OFFICIAL TRAVEL AGENT
Japan Travel Bureau, Inc.(JTB) has been appointed as the official travel
agent for the conference to handle conference registrations, hotel
accommodations, accompanying persons' programs and tours in Kyoto should be
addressed to
JAPAN TRAVEL, BUREAU, Inc.
Kyoto Office
Convention Department,
Higashi shiokoji-cho, Shimogyo-ku,
KYOTO 600, Japan
Phone : 81(JAPAN) 75-361-7241
Fax : 81(JAPAN) 75-341-1028
Telex : 5422014
FOREIGN EXCHANGE AND TRAVELERS CHECKS
It is recommended that participants purchase travelers checks in
Japanese Yen or U.S. Dollars before leaving their own countries. The Secretariat
will accept only Japanese Yen in cash. Foreign currency exchange is available at
the banks in the New Tokyo International Airport, the Osaka International
Airport, and also at major hotels.
CLIMATE AND CLOTHING
The climate in Kyoto in October is generally pleasant, the average
temperature being 63F (17C). Participants are advised to being a light sweater
or raincoat since it can become chilly at night or when it rains.
KYOTO
The ancient capital of Japan, Kyoto nestles among picturesque mountains
and placid waters. Since its establishment as the seat of the imperial court
late in the 8th century, the city has prospered as a center of polities,
economy, culture, and arts. With its innumerable cultural treasures and its
traditional crafts, Kyoto has never ceased to attract visitors from around Japan
and throughout the world. Today it is a modern metropolis with an international
flavor; indeed, perhaps nowhere else in Japan can one so easily encounter the
past in the midst of an urban culture so eagerly preparing for the 21st century.
ACCESS TO KYOTO
Transportation to Kyoto from abroad is diagramed below : The most
convenient and economical means is to take the direct flight to Osaka
International Airport, where Airport limousines which depart every 20 min. , can
reach Kyoto in one hour. The participants who arrive at New Tokyo International
Airport (Narita) have a choice of the following three ways :
1. Take a domestic flight to Osaka from Narita, though there are few
flights available.
2. Take a domestic flight to Osaka from Haneda, following a 2-hour
airport limousine transfer from Narita. About 15 flights are available from
Haneda to Osaka each day.
3. Take a bullet train (Shinkansen) to Kyoto from Tokyo. Trains leave
every 15 min. and take 3 hours to reach Kyoto station.
( Airport limousines are available from Narita to Tokyo Station, 100
min. )
HOTEL ACCOMMODATION
A sufficient number of rooms have reserved at Kyoto Tokyu Hotel in
Kyoto. Reservation should be made by completing and returning the attached
application form, indicating the class and number of rooms desired. No
reservation will be confirmed in the absence of a deposit ( \10,000 per person
).
Hotel assignments will be made on a first-come, first-served basis.
Daily room charges are as follows :
Name of Hotel Class Room Charge
Twin/Bath Single/Bath
A 23,000 14,500
Kyoto Tokyu Hotel B 21,000 12,000
C 11,000
* The above rates include tax, service charges and breakfast.
CANCELLATION
In the case of hotel cancellation, written notification should be sent
to JTB. The deposit will be refunded after deducting the following cancellation
charges.
When the notification is reserved by JTB :
Up to 9 days before the first night of stay - \1,000
2 - 8 days before - 50% of daily room
rate
Less than 2 days before, or no notice given - 100% of the daily
room rate
CONFERENCE FEE
The following registration fees are applicable for the conference :
regular student
15,000 5,000
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Registration and Hotel Accommodation Form
Please fill in this form ( English block letter only ) and return this form
before to :
JAPAN TRAVEL BUREAU
Kyoto Office Convention Dept. ( SASIMI '90 )
Higashi Shiokoji-cho
Shimogyo-ku, Kyoto, Japan
FAX : 81(JAPAN) 75-341-1028
Prof. Dr. Mr. Mrs. Ms.
Family Name First Name Middle Initial
Affiliation
Mailing address
Street City State
Country Zip Code
Telephone Telex
Fax E-mail
Registration Fee
regular student amount
q \15,000 q \5,000 \ (a)
Hotel Accommodations
Kyoto Tokyu Hotel Class A Class B Class C
Twin Room q \23,000 q \21,000
(price for 2 persons)
Single Room q \14,500 q \12,000 q \11,000
Check-in Date : Oct. , 1990
Check-out Date : Oct. , 1990 = night(s)
Hotel Deposit : room * \10,000 = \ (b)
Total amount due( total(a)+(b) ) : \
Payment
Payment if fees should be made in Japanese currency (yen). Please
indicate which of the following means of payment you intend to use :
q I enclose herewith a bank draft, coverint the above total, payble to
the order of
q I would like to pay the above total by the following credit card :
Record of Charges
Total Amount : \
Name of Card : q Diners
q Master Card
q VISA
q American Express
Card No :
Expire date :
Card Member Signature :
Payment or proof payment should accompany this form. In case it is
impossible to send fees beforehand, please attach a letter to this form,
explaning reasen.
Date : Signature :
This application will be valid upon your receiving
confirmation from JTB.
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