ieevlsi1@caesar.cs.montana.edu (Bob Wall) (02/22/90)
This is a rather lengthy posting that OCT users may be interested in. My
condolences to non-OCT types.
This may not be news to many of you, but we have discovered a relatively
straight-forward means of tiling arrays of custom cells constructed in the
OCT database using the BDNET tool.
Bdnet is a tool provided with OCT which allows structural descriptions of
circuits to be specified. That is, it allows the user to specify cells,
their placement, and their interconnection, as opposed to a behavioral
description of the circuit (like that created using bds, another OCT tool),
which allows the user to specify the functional relationship between the
inputs and outputs of the circuit without describing its internal
organization.
We have found a means by which bdnet can be used to specify the placement
and orientation of both symbolic and physical cells in the OCT environment.
As an example, we created a simple inverter using the VEM layout editor,
and then used bdnet to create a string of three of them, using this input
file:
INPUT
in1:temp<0>;
OUTPUT
out1:temp<3>;
ARRAY %x FROM 0 to 2 OF
INSTANCE inv:physical [%x * 500, 0]
in:temp<%x>;
out:temp<%x+1>;
which is just a simple bdnet description, where we added the position
specifier ([%x * 500, 0]) to each instance. Note that the position can be
specified using algebraic expressions, making tiling in one or two
dimensions fairly easy. The position is specified in OCT units, which are
typically 1/20th of a lambda. For this example, the inverter cell was 25
lambdas wide, so we used 500 OCT units as the distance between corresponding
points within successive instances.
It is also possible to rotate and mirror objects that are being placed,
using the predefined bdnet constants OCT_ROT90, OCT_ROT180, OCT_ROT270,
OCT_MIRROR_X, OCT_MIRROR_Y, OCT_MX_ROT90, AND OCT_MY_ROT90 in the
positional specification. For example, we changed the INSTANCE command in
the above description to
INSTANCE inv:physical [%x * 500, 0, OCT_MIRROR_X]
to flip each element about the Y axis (mirrors about X = 0). The result is
the same string of three inverters, but they "point" the other direction.
We also used bdnet to tile an instance of a standard cell from the Mississipi
State library. We created an 8x8 array of shift registers with the file
INPUT clk1,q<0>,q<9>,q<18>,q<27>,q<36>,q<45>,q<54>,q<63>;
OUTPUT q<8:1>,q<17:10>,q<26:19>,q<35:28>,q<44:37>,q<53:46>,
q<62:55>,q<71:64>;
SUPPLY Vdd;
GROUND GND;
ARRAY %j FROM 0 TO 7 OF
ARRAY %i FROM 0 TO 7 OF
INSTANCE "~cad/lib/technology/scmos/msu/dlm/1830":physical
[%i*1760,%j*2240]
1DATA:q<%i+9*%j>;
2CLK:clk1;
Q:q<%i+1+9*%j>;
QB:UNCONNECTED;
"VDD":Vdd;
"GND!":GND;
The size of each shift register was 88x112 lamdas, giving an OCT spacing of
1760x2240.
We verified that this method could be used on symbolic circuits as well.
We built a simple non-functional cell using the VEM symbolic editor
(thing:symbolic), and created a 3x3 array using the bdnet input file
INPUT
nin<0>:n<0>, nin<1>:n<4>, nin<2>:n<8>,
ein<0>:e<0>, ein<1>:e<4>, ein<2>:e<8>,
win<0>:w<3>, win<1>:w<7>, win<2>:w<11>,
sin<0>:s<3>, sin<1>:s<7>, sin<2>:s<11>;
OUTPUT
nout<0>:n<3>, nout<1>:n<7>, nout<2>:n<11>,
eout<0>:e<3>, eout<1>:e<7>, eout<2>:e<11>,
wout<0>:w<0>, wout<1>:w<4>, wout<2>:w<8>,
sout<0>:s<0>, sout<1>:s<4>, sout<2>:s<8>;
ARRAY %x FROM 0 to 2 OF
ARRAY %y FROM 0 to 2 OF
INSTANCE thing2:symbolic [%x * 1200, %y * 1200]
nin:n<%x*(3+1)+%y>;
ein:e<%y*(3+1)+%x>;
win:w<%y*(3+1)+%x+1>;
sin:s<%x*(3+1)+%y+1>;
nout:n<%x*(3+1)+%y>;
eout:e<%y*(3+1)+%x>;
wout:w<%y*(3+1)+%x+1>;
sout:s<%x*(3+1)+%y+1>;
The "thing" was 60x60 lambdas, giving a spacing in OCT units of 1200x1200.
This provides a fairly easy to tile homogeneous regular arrays of cells,
instancing either physical or symbolic views, using bdnet. There are a
few points which could be addressed to make it easier to use: the user must
know the dimensions of the cell to be tiled; it is necessary to create
temporary "internal nodes" to be used by bdnet to connect together outputs
of one cell and inputs of the next cell; and it is necessary for the user to
do the arithmetic to calculate the indices used to connect each instance's
inputs and outputs to the correct internal node. None of these problems are
that difficult to work around, and it should be easy to write a program which
could take a circuit specification, check the cells instanced to find out
their dimensions, and generate a bdnet input file with everything automati-
cally calculated. This would greatly enhance its usability as a tiler.
For those C hackers out there who would like a more sophisticated means of
tiling, the OCT tool suite comes with a package of routines called MKARRAY.
These routines provide a means of accessing the OCT database and assembling
modules of cells. A substantial amount of work would be necessary to put
together a tool to tile datapaths.
Send any questions, comments, curses, or other messages to me (Bob Wall)
--
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ieevlsi1@caesar.cs.montana.edu (Bob Wall EE Dept. Montana State U.)
"They've put an end to pain and sorrow; Real life shall resume tommorrow"
- Timbuk 3