jukka@stek9.oulu.fi (Jukka A. Lahti) (10/23/90)
I'm compiling information on logic synthesis systems for my thesis. Below is a list of those (non-commercial) systems I have found references of. Each entry contains the place the system was developed at, a short description and a reference to an article describing the system. I haven't been able to find all the original papers, so the list probably contains mistakes. Some note-worthy systems are probably missing, too. So, if you find some information on the list that is incorrect, or if your system is not mentioned, let me know, so I can put together a more complete list. If there is enough interest, I will post the complete list to the net. The systems I've listed are all logic synthesis tools, but I'd be interested of other kinds of systems (analog-synthesis, are there any ?), too. Reply by email, my address is below. Thanks in advance! Jukka Lahti (jukka@steks.oulu.fi) Phone: +358-81-352756 University of Oulu, Electronics Lab. Telefax: +358-81-561278 SF-90570 Oulu, FINLAND ------------------ C U T ------ H E R E --------------------- BDSYN - University of California, Berkeley, USA - FSM synthesis from DECSIM language for multilevel combination-logic realization - Brayton, R.: "Multiple-level Logic Optimization System", Proc. of IEEE ICCAD, Santa Clara, Nov. 1986 BECOME - AT & T Bell Labs, USA - FSM synthesis from C-like language for PLA, PLD and standard cell realization - Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414, IEEE, 1988 BOLD - logic optimization - Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10, October 1986 Bridge - AT & T Bell Labs, USA - (mostly) FSM-synthesis from FDL2-language descriptions - Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988 CADDY - Karlsruhe University, Germany - behavioral synthesis from DSL-language, based on data-flow analysis - Camposano, R.: "Synthesizing Circuits From Behavioral Descriptions", IEEE Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989 CARLOS - Karlsruhe University, Germany - multilevel logic optimization for CMOS realizations - Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for CMOS Semi-Custom Integrated Circuits", IEEE Transactions on Computer-Aided Design, Vol 7, No 3, pp. 346-355, March 1988 Cathedral - Univ. of Leuve, Phillips ja Siemens, Belgium - synthesis of DSP-circuits from algorithm descriptions - De Man, H.: "Architecture-Driven Synthesis Techniques for VLSI Implementation of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319, February 1990 CMU-DA - Carnagie-Mellon University, USA - behavioral synthesis from ISPS - Thomas, D.: "Linking the Behavioral and Structural Domains of Representation for Digital System Design", IEEE Transactions on Computer-Aided Design, pp. 103-110, Vol. 6, No. 1, January 1987 CONES - AT & T Bell Labs, USA - FSM synthesis, produces 2-level logic realizations (truth-table) - Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara, Nov. 1986. Design Automation Assistant (DAA) - AT & T Bell Labs, USA - expert system for datapath synthesis - Kowalski, T.J. " The VLSI Design Automation Assistant: An Architecture Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988 Flamel - AT & T Bell Labs, USA - datapath and control-logic synthesis from Pascal description - Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions on Computer-Aided Design, Vol 6, No 2, March 1987. HAL - Carleton University, Canada - datapath synthesis - Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661, Vol. 8, No. 6, June 1989 Hercules - Stanford University, USA - behavioral synthesis from C-language - De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988 LSS (Logic Synthesis System) - IBM, USA - logic synthesis and optimization from many RTL-languages - Darringer, J. et al. "LSS: A System for Production Logic Synthesis", IBM Journal of Research and Development, vol. 28, No. 5, pp. 272-280, Sept 1984. MAHA - University of Southern California, USA - datapath synthesis - Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE Design Automation Conference, pp. 252-258, IEEE 1986. MIS - University of California, Berkeley, USA - multilevel logic optimization - Brayton, R.K. "MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on Computer-Aided Design, Vol. 6, No. 6, November 1987. pp. 1062-1081 SEHWA - University of Southern California, USA - pipeline-realizations from behavioral descriptions - Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE Design Automation Conference, pp. 454-460, IEEE 1986. Socrates - General Electric, University of Colorado, USA - expert system - logic optimization and mapping for different technologies - de Geus, A.J., "The Socrates Logic Synthesis and Optimization System", Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers, 1987. SPAID - Waterloo University, Canada - DSP-synthesis for silicon compiler realizations - Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989. System Architects Workbench - Carnagie-Mellon University, USA - behavioral synthesis - Thomas, D. "The System Architect's Workbench", Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988 Yorktown Silicon Compiler - IBM T.J.Watson Research Centre, USA - datapath synthesis, logic synthesis etc. - Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation, pp. 204-311, Addison-Wesley, 1988 -- ------------------------------------------------------------------------ Jukka Lahti (jukka@steks.oulu.fi) Phone: +358-81-352756 University of Oulu, Electronics Lab. Telefax: +358-81-561278 SF-90570 Oulu, FINLAND
jamesth@microsoft.UUCP (James THIELE) (10/25/90)
Please post the final list. It would be appreciated. Thanks, James Thiele -- microsoft!jamesth