[comp.lsi.cad] Automatic transistors sizing

vuillamy@eecg.toronto.edu (Jean-Michel Vuillamy) (10/26/89)

In the paper "High-Speed CMOS Circuit technique" (IEEE Journal of Solid-State
Circuits, Vol 24 n. 1, February 1989), the authors J.Yuan and C. Svensson are
describing some tools for automatic optimization through device sizing. Two 
programs are mentioned : SLOP and TMODS.

Could you mail me some information about those tools (or any others : I would
be interested in public domain software). If I'll get enough answers, I will
publish them later.

			Jean-Michel Vuillamy

pi@susan.isi.edu (Jen-I Pi) (10/27/89)

In article <1989Oct26.115326.19494@jarvis.csri.toronto.edu>,
vuillamy@eecg.toronto.edu (Jean-Michel Vuillamy) writes:
> In the paper "High-Speed CMOS Circuit technique" (IEEE Journal of Solid-State
> Circuits, Vol 24 n. 1, February 1989), the authors J.Yuan and C. Svensson are
> describing some tools for automatic optimization through device sizing. Two 
> programs are mentioned : SLOP and TMODS.
> 
> Could you mail me some information about those tools (or any others : I would
> be interested in public domain software). If I'll get enough answers, I will
> publish them later.
> 
> 			Jean-Michel Vuillamy


Here is what I know, hope it is helpful ....

(1) TMODS is s dynamic switch-level simulator (here dynamic means more than one
    signals can propagate in the circuit simutaneously). It has five
logic states:
    
      H : High,   U : Up,   X : Undetermined,   D : Down,   L : Low.

    Only two types of transistors are modeled: n-MOS and p-MOS. It use
an extented
    local relaxation (ELR) algorithm to calculate only those nodes whose states
    are changed.

    The 50-percent delay between input and output signal is represented by:

		Td  = A * Sr + B * Sf

    where Sr and Sf are input signal rising and falling slope respectively,
    and A and B are constant determined from SPICE simulation. For details,
    see [1].

(2) SLOP (Switch Level Optimization) is a transistor sizing tool at
switch level.
    The delay model in SLOP is more complex than that in TMODS [more than two
    constants are involvoed :-)]. The point is that delay will be a
convex function
    of transistor width by the use of this model. Thus a global optimal
solution
    is POSSIBLE. For details see [2].

I am not sure whether TMODS or SLOP is in the publick domain. However I would
suggest waiting for the next release of Magic (version 6) from Bob Mayo from
DEC's Western Research Lab. where an improved switch-level simulator (irsim)
based on MIT's RSIM and Chorng-Yeoung Chu's (Stanford) model [3] is included.
It also comes with an excellent X-Window Interface and PosrScript plot utility.

References:
@string{iscas = "Proceedings of International Symposium on Circuits and
Systems"}
@string{ieeetcad = "{IEEE} Transactions on Computer-Aided Design"}
[1]
@article{Sundblad87,
  author="R. Sundblad and C. Svensson",
  title="Fully {D}ynamic {S}witch-{L}evel {S}imulation of {CMOS} {C}ircuits",
  journal=ieeetcad,
  year=1987,
  volume="CAD-6",
  number=2,
  pages={282--289}
}
[2]
@inproceedings{Yuan88,
  author="J. Yuan and C. Svensson",
  title="{CMOS} {C}ircuit {S}peed {O}ptimization {B}ased on {S}witch {L}evel\
	{S}imulation",
  booktitle=iscas,
  year=1988,
  pages={2109--2112},
  organization="IEEE"
}
[3]
@techreport{Chu88,
  author="Chorng-Yeong Chu",
  title="Improved {M}odels for {S}witch-{L}evel {S}imulation",
  institution="Stanford University",
  year=1988,
  number="CSL-TR-88-368",
  month="Nov."
}

Jen-I pi@vlsi-cad.isi.edu :-)
MOSIS Project, USC/ISI