mikel@mcnc.org (Michael J. Lorenzetti) (03/23/89)
_S_I_G_D_A _F_u_n_d_s _C_A_D _B_e_n_c_h_m_a_r_k _D_i_s_t_r_i_b_u_t_i_o_n _t_h_r_o_u_g_h _M_C_N_C
Michael Lorenzetti (SIGDA Secretary/Treasurer)
Jeri Williams (MCNC)
Recognizing the importance of standardized examples in com-
paring CAD algorithms, SIGDA (the ACM Special Interest Group
on Design Automation) is providing funding for The
Microelectronics Center of North Carolina (MCNC) to act as a
CAD benchmark distribution center. These benchmarks consist
of sets of design data which are inputs to DA programs.
They allow researchers to compare results on a common set of
problems and thereby more clearly identify advantages of
particular algorithms or techniques.
The benchmarks available under this program are:
Benchmarks Source
_______________________________________________________________________
Module Generation Physical DA Workshop, 1989
Place and Route Physical DA Workshop, 1987
and MCNC Workshop, 1988
Logic Synthesis MCNC Workshop, 1987 and 1989
Symbolic Layout and Compaction MCNC Workshop, 1986
Test Generation (combinational logic) ISCAS 85
Test Generation (sequential logic) ISCAS 89
High Level Synthesis SIGDA Workshop, 1989
(still in development)
The _M_o_d_u_l_e _G_e_n_e_r_a_t_i_o_n benchmarks contain transistor net-
lists for several modules including circuits such as ALU's
and RAM's. The _P_l_a_c_e _a_n_d _R_o_u_t_e benchmarks contain standard
cell, gate array and building block layout examples. See
the Proceedings of the 24th ACM/IEEE Design Automation
Conference, pp. 319-320 for a summary of standard cell and
gate array examples. The _L_o_g_i_c _S_y_n_t_h_e_s_i_s benchmarks con-
tain examples from two-level logic in PLA (ESPRESSO) format,
finite-state tables in KISS or ESPRESSO-MV format and
multi-level logic in BLIF or Netlist-BLIF format. The _S_y_m_-
_b_o_l_i_c _L_a_y_o_u_t _a_n_d _C_o_m_p_a_c_t_i_o_n benchmarks are nmos and cmos
examples of symbolic layout and compaction. The _T_e_s_t _G_e_n_-
_e_r_a_t_i_o_n (combinational logic) benchmarks are a set of 10
combinational circuits used for comparing the results of
test pattern generation software. The circuits range in size
from 160 gates to over 3500 gates, and include several
arithmetic and error correcting and translation circuits.
The _T_e_s_t _G_e_n_e_r_a_t_i_o_n (sequential logic) benchmarks are a set
of 31 sequential circuits used for comparing the results of
test pattern generation software. The smallest circuit has
10 gates and 3 D flip-flops and the largest has over 22,000
gates and 1700 D flip-flops. They are real designs taken
from several commercial and academic institutions. The
_H_i_g_h _L_e_v_e_l _S_y_n_t_h_e_s_i_s benchmarks are behavioral descriptions
written in in VHDL.
This list of benchmarks will be expanded as future workshops
are held and benchmark sets developed.
The benchmarks are made available by FTP over arpanet or by
9-track tar-tapes. There is no charge for this service as
SIGDA covers all tape and mailing costs. To obtain any of
the benchmarks, send electronic mail to
"benchmarks@mcnc.org" or write to
Jeri Williams
MCNC
P.O. Box 12889
Research Triangle Park, NC 27709.
SIGDA and MCNC are enthusiastic about the benchmarks pro-
gram. We feel that it advances the state-of-the-art of
Design Automation by providing a vehicle for meaningful com-
parisons among a wide variety of researchers.
At the present time neither SIGDA nor MCNC are collecting or
scoring the results of these benchmarks. Instead, we
encourage researchers to cite their results on these exam-
ples when they publish their research. This is already hap-
pening in a big way with the place and route benchmarks (see
the 24th and 25th DAC proceedings). Although a central
scoring procedure would encourage competition, not having
one prevents arbitrary emphasis of one citeria over another
(e.g. speed vs. area) and allows researchers to point up
advantages of particular algorithms in making these trade-
offs.