jukka@stek9.oulu.fi (Jukka A. Lahti) (08/22/90)
I'd like to know what kind of syntax Synopsys accepts for Finite State Machine descriptions. We are planning to build an interface from our graphical FSM design system to Synopsys. We are currently using VHDL as a description language. What subset of VHDL does Synopsys use ? Any help would be appreciated. BTW, is anybody from Synopsys on the net ? ----------------------------------------------------------------------------- * Jukka Lahti * * University of Oulu (email: jukka@steks.oulu.fi) * * Dept. of Electrical Engineering * * Electronics Laboratory * * SF-90570 OULU * * Finland * ------------------------------------------------------------------------------