johnh@babel.SanDiego.NCR.COM (John Holmes) (09/07/89)
We are considering bringing our ECL ASIC placement and routing in house,
but are still in the very early stages of investigation of the issues.
Any experiences you may have as an end user doing gate array placement and
routing would be interesting. Especially ECL routing.
Some specific questions:
(please note if answering from experience or literature)
Do any tools do a good job of placing/routing clock trees in large circuits?
Did in-house P&R shorten the overall design cycle?
What commercial or university tools do a good job with ECL arrays?
Was the tool provided by the foundry or third party?
If the tool was third party, what was involved in getting set up with
the ASIC vendor's chips?
All answers will be much appreciated,
John.