[comp.lsi.cad] Need gate level logic simulator

siu@Data-IO.COM (From: siu@fnrsun.Data-IO.COM (Denny Siu)) (07/10/90)

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References: <1990Jun18.025334.7298@monu6.cc.monash.edu.au> <14012@venera.isi.edu> <24@pubit.sublink.ORG>
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Reply-To: siu@fnrsun.Data-IO.COM (Denny Siu)
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Organization: Data-IO Corporation; Redmond, WA
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Does anyone know about any public domain gate level logic simulator that can
handle unit time delay. The primitive should not lower than AND or OR gate.
Can Csim or Rsim do the job, or they are tranistor level simulator?
Thank you in advance!