dmw@taurus.ece.cmu.edu (Hank Walker) (02/26/91)
1991 IEEE INTERNATIONAL WORKSHOP ON
DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS
November 18 - 20, Hidden Valley, Pennsylvania
CALL FOR PAPERS
The goal of this workshop is to provide a discussion forum for researchers
and practitioners dealing with digital, analog, and mixed VLSI integrated
circuits. All aspects of design, manufacturing, test, reliability, and
availability which are affected by defects during manufacturing and by
faults during system operation are of interest.
The scope of the workshop includes, but is not limited to, the following
topics:
Defect and fault tolerant architectures
Defect and fault tolerant memories
Defect and fault tolerant analog and mixed ICs
Case studies of defect and fault tolerance
Fault models and defect models
CAD tools
Techniques for yield enhancement
Statistical yield modeling
Repair and restructuring techniques
Technology issues for defect tolerant architectures
Packaging techniques for WSI, 3-D VLSI, and MCMs
On-line reconfiguration
Run-time fault modeling
Testable and self-testable designs for VLSI and WSI
Test coverage and test quality
Testing of mixed signal ICs
Three kinds of presentations are planned: tutorials (45 min. talk, 15 min.
discussion), regular papers (25 min. talk, 10 min. discussion), and short
presentations (5 min. description of current research or a problem to be
solved, 10 min. discussion). In addition, evening working groups for the
continuation of discussions initiated during the presentations will be
organized
General Chair: Program Chair:
Wojciech Maly D. M. H. Walker
Dept. of Electrical. and Comp. Eng. Dept. of Electrical and Computer Eng.
Carnegie Mellon University Carnegie Mellon University
Pittsburgh, PA 15213-3890 Pittsburgh, PA 15213-3890
USA USA
Tel: (412) 268-6637 Tel: (412) 268-8522
Fax: (412) 268-2860 Fax: (412) 268-2860
E-mail: maly@ece.cmu.edu E-mail: dmw@ece.cmu.edu
Program Committee:
V. K. Agarwal, McGill Univ., Canada M. Rivier, IBM, France
L. R. Carley, CMU, USA M. Sami, Politecnico di Milano, Italy
A. V. Ferris-Prabhu, IBM, USA G. Saucier, INPG, Grenoble, France
W. K. Fuchs, Univ. of Illinois, USA Y. Savaria, Ecole Polytechnique, Canada
V. K. Jain, Univ. South Florida, USA C. H. Stapper, IBM, USA
I. Koren, Univ. of Massachusetts, USA E. Swartzlander, Univ. of Texas, USA
R. M. Lea, Brunel Univ., UK J. P. Teixeira, INESC, Portugal
F. Lombardi, Texas A&M Univ., USA J. Trihle, SGS Thomson, France
T. Mangir, TRW, USA T. W. Williams, IBM, USA
W. Moore, Oxford, UK
INFORMATION FOR AUTHORS
Authors are invited to submit 21 copies of a regular paper or short
presentation no later than May 1, 1991 to the Program Chair. Regular paper
submissions should be a full paper of at least 10 pages, or an extended
summary of 5 pages of text plus an unlimited number of figures. Short
presentation submissions should be a two-page abstract. For regular papers,
preference will be given to full-length submissions. Proposals and requests
for tutorials, panel discussions, and working groups should be sent to the
General Chair as soon as possible, but no later than April 15, 1991.
Notification of acceptance will be posted by July 8, 1991. Final
manuscripts (20 pages including figures for tutorials, 14 pages including
figures for regular papers, and 3 pages including figures for short
presentations) must be received by August 30, 1991 for inclusion in the
workshop proceedings. A formal proceedings will be published by IEEE
Computer Society Press.
IMPORTANT DATES
May 1, 1991 Submission Deadline
July 8, 1991 Acceptance Notification
August 30, 1991 Final Manuscript Due
LOCATION
Hidden Valley is a resort in the Laurel Mountains about one hour east of
Pittsburgh. Shuttle bus transportation from the Pittsburgh International
Airport will be provided.
SPONSORSHIP
Sponsored by the IEEE Computer Society Technical Committee on Fault-Tolerant
Computing, in cooperation with the Technical Committee on VLSI, and
sponsored by the Solid State Circuits Council.