sergio@techunix.BITNET (Sergio Fogel) (11/02/90)
I am looking for references to a program (or algorithms) that receives the description of a logic circuit (purely combinatorial, with no cycles, if this helps) and produces a drawing of the circuit. What I need is a drawing easy for humans to read. Any help will be greatly appreciated. Sergio -- Sergio Fogel sergio@techunix.BITNET
ejmag@aplcen.apl.jhu.edu (Eric Magnusson) (11/03/90)
In article <9812@discus.technion.ac.il> sergio%techunix.bitnet@lilac.berkeley.edu (Sergio Fogel) writes: >I am looking for references to a program (or algorithms) that receives >the description of a logic circuit (purely combinatorial, with no cycles, >if this helps) and produces a drawing of the circuit. What I need is a >drawing easy for humans to read. > The Design Compiler by Synopsys Inc. (Mountain View, Calif.) will read a netlist, logic equations, state diagrams, or a hardware description language representation (like Verilog or VHDL) of a circuit. It can then map the circuit onto a generic or specific technology (like LSILogic or your own cell library). If you want you may optimize the circuit according to what specs you specify. Finally, you can output the design in any of the above formats, including a PostScript schematic of the circuit. The tool is pricey, but the only real way to do ASIC design. It can handle designs with combinatorial or sequential constructs. I know GenRad (UK & Mass.) just announced a tool which integrates with their cad environment and has similar capabilities, but I only have experience with the Synopsys tools. "The statements above represent the opinions and experiences of the author and may not necessarily represent the views of Synopsys Inc. or GenRad. Prices may vary. Batteries not included." Good Luck! -- Eric Magnusson ejmag@aplcen.apl.jhu.edu I was Bourne, Bourne, Bourne .... Bourne to be alive!!!!
hagerman@ece.cmu.edu (John Hagerman) (11/03/90)
sergio@techunix.BITNET (Sergio Fogel) writes:
From: sergio@techunix.BITNET (Sergio Fogel)
Reply-To: sergio%techunix.bitnet@lilac.berkeley.edu (Sergio Fogel)
I am looking for references to a program (or algorithms) that receives
the description of a logic circuit (purely combinatorial, with no cycles,
if this helps) and produces a drawing of the circuit. What I need is a
drawing easy for humans to read.
I've used the following algorithm for circuits containing a few dozen
parts (restricted to rectangles with pins on left and right sides):
1: "Levelize" the components for placement in columns. The simplest
way to do this is to start from each input and traverse the netlist
to find the shortest path to each component from an input. More
sophisticated and pleasing levelizations are easy to think of.
2: Order the components in each column for placement in rows. Doing
this well is difficult. The goal is to minimize the number of nets
that have to run vertically. I have used a recursive mincut method
that works OK. A force-directed method might also be used.
3: Order the column of inputs (on the left) and the column of outputs
(on the right) to minimize net crossings.
4: Draw the components in rows and columns, leaving space for routing
tracks. It's easiest to leave a fixed amount of space, although
you will probably have to leave more space than you'd like to. I
draw pins on the components, and also for inputs and outputs.
5: Draw horizontal "stubs" from the pins of the components and the
input and output pins. The main task here is to assign nets to
routing tracks running vertically between columns of components.
The stubs "connect" pins to the routing tracks.
6: Draw horzontal routing segments between rows of components. Again,
nets are assigned to routing tracks running horizontally between
rows of components. The horizontal segments are used to connect
the vertical routing tracks.
7: Draw vertical segments from the stubs to the horizontal segments.
This completes the routing.
Another thing to deal with is crossing versus connected intersections
of segments. It's easiest to just draw dots for connections and not
to worry about fancy symbolism for unconnected crossings.
Brute-force data structures and algorithms are sufficient (if you have
a reasonably fast machine). For example, when assigning a net to a
horizontal track, I first compute the necessary extent, and then try
horizontal tracks until I find one that no other net is using on the
desired extent. This is a gross method, since all nets are examined
for each track tried, but it's still fast enough.
- John
--
hagerman@ece.cmu.educhristos@batcomputer.tn.cornell.edu (Christos S. Zoulas) (11/03/90)
In article <9812@discus.technion.ac.il> sergio%techunix.bitnet@lilac.berkeley.edu (Sergio Fogel) writes: >I am looking for references to a program (or algorithms) that receives >the description of a logic circuit (purely combinatorial, with no cycles, >if this helps) and produces a drawing of the circuit. What I need is a >drawing easy for humans to read. I wrote something like that a while ago. I did not want to distribute it before I was done, but since there seems to be a demand for it I'll put a copy on tesla.ee.cornell.edu, in /pub/biz.tar.Z. It is not production quality code, and there are some more things I'd like to implement, but I will make it public now... My program is a type of lint(1), for .sim format files and it produces plotting information that can be translated to tgif, or directly plotted on X. We use it here at Cornell to reverse-engineer and debug magic layouts. If you do get a copy, I would appreciate it if you'd drop me a line and give me your e-mail address, so I can keep track of things and notify you about updates. christos -- /------------------------------------------------------------------------\ | Christos Zoulas | 409 Phillips Hall, Electrical Engineering, | | christos@ee.cornell.edu | Cornell University, Ithaca NY 14853. | | christos@crnlee | Phone: (607) 255 4323 | Fax: (607) 254 4565 |