amblard@imag.imag.fr (Paul Amblard) (11/23/89)
I am looking for users of the language MODEL... I teach computer architecture, logic synthesis and VLSI design at the University of Grenoble (France). For the practical activities my students (and I ..) use a CAD package called SOLO 1x00 ( 1st version : solo1000, then solo1200, now solo 1400) This is a silicon compiler, the "host" structure is a cell array enhanced with RAM, ROM PLA and CN/A CA/N pads. This software is distributed in Europe by a firm called ES2, in USA by US2 (European/United Silicon Structures). The system allows the description by two ways : graphical interface or textual descrition with the language MODEL. IF YOU USE model, MAIL ME... we could exchange exemples, tricks, ideas.. If you do not use it just know that a part of the ES2 system is originated in a tool previously distributed by LATTICE LOGIC. Somme references : 22nd DAC, p597-601 : portability in silicon CAE, by JP GRAY J HUNTER ; p591-596 : a case study in process independence by N ROYAL , J HUNTER, I BUCHANAN ; 19th DAC p377-383 designing gate arrays using a silicon compiler by JP GRAY, I BUCHANAN, P ROBERTSON. I do not have relations with neither ES2 nor Lattice logic . I am just a satisfied user. May our future collaboration be fruitfull ... Ciao -- Paul AMBLARD | amblard@imag.imag.fr L.G.I. I.M.A.G. | amblard@imag.UUCP BP 53X | (uunet.uu.net!imag!amblard) F 38041 GRENOBLE Cedex ! Tel 76514600 ext 5144
M.Nigri@ucl-cs.UUCP (12/21/89)
From: "Meyer E. Nigri" <M.Nigri@uk.ac.ucl.cs>
Dear Paul,
I am a Research Student at University College London
working with Silicon Compilation with a special interest in
Neural Networks. I am currently considering the usage of VHDL
as an intermediate step between the neural network
specification language and its hardware implementation
(probably using SOLO 2XXX).
I read your message in a bulletin board. I know
nothing about MODEL, but here in UCL we are using SOLO 2XXX,
which uses EDIF as the input language. (What is the connection
between MODEL and EDIF ?)
Do you know if there is any software tool that inputs
VHDL, rather than EDIF or MODEL, into SOLO. Or any software
that maps VHDL into EDIF or MODEL ?
I look forward to exchange ideas with you.
Yours sincerely,
Meyer.
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|Meyer Elias Nigri | JANET:mnigri@uk.ac.ucl.cs |
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